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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036288/0748   Pages: 247
Recorded: 08/06/2015
Attorney Dkt #:70341.00400
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1836
Page 2 of 19
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1
Patent #:
Issue Dt:
05/06/2008
Application #:
10882078
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD AND APPARATUS FOR FLIP CHIP ATTACHMENT BY POST COLLAPSE RE-MELT AND RE-SOLIDIFICATION OF BUMPS
2
Patent #:
Issue Dt:
07/10/2007
Application #:
10894561
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
01/19/2006
Title:
INTEGRATED CIRCUIT DIE WITH PEDESTAL
3
Patent #:
Issue Dt:
07/10/2007
Application #:
10906697
Filing Dt:
03/02/2005
Publication #:
Pub Dt:
09/07/2006
Title:
STACKED SEMICONDUCTOR PACKAGES AND METHOD THEREFOR
4
Patent #:
Issue Dt:
06/03/2008
Application #:
10907732
Filing Dt:
04/13/2005
Publication #:
Pub Dt:
10/19/2006
Title:
INTEGRATED CIRCUIT SYSTEM FOR BONDING
5
Patent #:
Issue Dt:
03/04/2008
Application #:
10907758
Filing Dt:
04/14/2005
Publication #:
Pub Dt:
10/19/2006
Title:
LEADFRAME WITH ENCAPSULANT GUIDE AND METHOD FOR THE FABRICATION THEREOF
6
Patent #:
Issue Dt:
07/03/2007
Application #:
10907991
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
SYSTEM FOR PEELING SEMICONDUCTOR CHIPS FROM TAPE
7
Patent #:
Issue Dt:
12/12/2006
Application #:
10908120
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING AND FABRICATION METHOD THEREFOR
8
Patent #:
NONE
Issue Dt:
Application #:
10908254
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
11/03/2005
Title:
INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
9
Patent #:
Issue Dt:
05/22/2007
Application #:
10908433
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
11/16/2006
Title:
SELF-ALIGNING DOCKING SYSTEM FOR ELECTRONIC DEVICE TESTING
10
Patent #:
Issue Dt:
06/03/2008
Application #:
10913806
Filing Dt:
08/05/2004
Publication #:
Pub Dt:
02/09/2006
Title:
METHOD AND APPARATUS FOR STACKED DIE PACKAGING
11
Patent #:
Issue Dt:
11/01/2005
Application #:
10914870
Filing Dt:
08/09/2004
Publication #:
Pub Dt:
01/13/2005
Title:
SEMICONDUCTOR DEVICE PACKAGE
12
Patent #:
Issue Dt:
07/03/2012
Application #:
10921376
Filing Dt:
08/18/2004
Publication #:
Pub Dt:
03/03/2005
Title:
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
13
Patent #:
Issue Dt:
01/04/2011
Application #:
10921377
Filing Dt:
08/18/2004
Publication #:
Pub Dt:
03/03/2005
Title:
ARRAY-MOLDED PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
14
Patent #:
Issue Dt:
09/13/2005
Application #:
10931654
Filing Dt:
08/31/2004
Title:
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
15
Patent #:
Issue Dt:
06/20/2006
Application #:
10931919
Filing Dt:
08/31/2004
Publication #:
Pub Dt:
03/02/2006
Title:
STACKED DIE PACKAGING AND FABRICATION METHOD
16
Patent #:
Issue Dt:
11/29/2005
Application #:
10934129
Filing Dt:
09/02/2004
Title:
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE SYSTEM
17
Patent #:
NONE
Issue Dt:
Application #:
10934835
Filing Dt:
09/02/2004
Publication #:
Pub Dt:
03/02/2006
Title:
Wire sweep resistant semiconductor package and manufacturing method thereof
18
Patent #:
Issue Dt:
07/11/2006
Application #:
10959713
Filing Dt:
10/06/2004
Publication #:
Pub Dt:
09/08/2005
Title:
DBG SYSTEM AND METHOD WITH ADHESIVE LAYER SEVERING
19
Patent #:
Issue Dt:
12/27/2005
Application #:
10969361
Filing Dt:
10/19/2004
Publication #:
Pub Dt:
03/10/2005
Title:
INTEGRATED CIRCUIT PACKAGE
20
Patent #:
Issue Dt:
08/05/2008
Application #:
10971202
Filing Dt:
10/22/2004
Publication #:
Pub Dt:
10/06/2005
Title:
WIRE BOND CAPILLARY TIP
21
Patent #:
Issue Dt:
12/11/2007
Application #:
10976601
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
09/22/2005
Title:
SEMICONDUCTOR CHIP PACKAGING METHOD WITH INDIVIDUALLY PLACED FILM ADHESIVE PIECES
22
Patent #:
Issue Dt:
01/26/2010
Application #:
10977047
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
10/06/2005
Title:
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
23
Patent #:
Issue Dt:
04/25/2006
Application #:
10983898
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/12/2005
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
24
Patent #:
Issue Dt:
05/06/2008
Application #:
10985654
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/26/2005
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
25
Patent #:
Issue Dt:
12/18/2007
Application #:
10986510
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
04/28/2005
Title:
STACKED SEMICONDUCTOR PACKAGES
26
Patent #:
Issue Dt:
08/15/2006
Application #:
10993526
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
04/28/2005
Title:
SEMICONDUCTOR PACKAGES AND LEADFRAME ASSEMBLIES
27
Patent #:
Issue Dt:
09/17/2013
Application #:
11007896
Filing Dt:
12/08/2004
Publication #:
Pub Dt:
12/01/2005
Title:
INTEGRATED CIRCUIT LEADFRAME AND FABRICATION METHOD THEREFOR
28
Patent #:
Issue Dt:
08/12/2008
Application #:
11009436
Filing Dt:
12/09/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR SOLDER BUMPING, AND SOLDER-BUMPING STRUCTURES PRODUCED THEREBY
29
Patent #:
Issue Dt:
03/03/2015
Application #:
11014257
Filing Dt:
12/16/2004
Publication #:
Pub Dt:
06/23/2005
Title:
Multiple chip package module having inverted package stacked over die
30
Patent #:
Issue Dt:
08/07/2007
Application #:
11022375
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
01/19/2006
Title:
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
31
Patent #:
Issue Dt:
04/06/2010
Application #:
11027002
Filing Dt:
12/31/2004
Publication #:
Pub Dt:
07/21/2005
Title:
DIE ATTACH BY TEMPERATURE GRADIENT LEAD FREE SOFT SOLDER METAL SHEET OR FILM
32
Patent #:
NONE
Issue Dt:
Application #:
11035637
Filing Dt:
01/14/2005
Publication #:
Pub Dt:
07/20/2006
Title:
Under bump metallurgy in integrated circuits
33
Patent #:
Issue Dt:
06/30/2009
Application #:
11053564
Filing Dt:
02/07/2005
Publication #:
Pub Dt:
08/10/2006
Title:
MULTI-LEADFRAME SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
34
Patent #:
Issue Dt:
09/05/2006
Application #:
11059274
Filing Dt:
02/16/2005
Publication #:
Pub Dt:
07/07/2005
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA) PACKAGE
35
Patent #:
Issue Dt:
01/30/2007
Application #:
11121847
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
11/09/2006
Title:
SEMICONDUCTOR PACKAGE WITH SELECTIVE UNDERFILL AND FABRICATION METHOD THERFOR
36
Patent #:
Issue Dt:
11/20/2007
Application #:
11126052
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
11/09/2006
Title:
LARGE DIE PACKAGE AND METHOD FOR THE FABRICATION THEREOF
37
Patent #:
Issue Dt:
10/08/2013
Application #:
11134845
Filing Dt:
05/20/2005
Publication #:
Pub Dt:
12/08/2005
Title:
ADHESIVE/SPACER ISLAND STRUCTURE FOR STACKING OVER WIRE BONDED DIE
38
Patent #:
Issue Dt:
05/01/2007
Application #:
11145246
Filing Dt:
06/03/2005
Publication #:
Pub Dt:
10/06/2005
Title:
SELF-COPLANARITY BUMPING SHAPE FOR FLIP CHIP
39
Patent #:
Issue Dt:
08/05/2008
Application #:
11145247
Filing Dt:
06/03/2005
Publication #:
Pub Dt:
10/06/2005
Title:
Self-coplanarity bumping shape for flip chip
40
Patent #:
Issue Dt:
11/04/2008
Application #:
11160837
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
03/02/2006
Title:
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
41
Patent #:
Issue Dt:
06/08/2010
Application #:
11162617
Filing Dt:
09/16/2005
Publication #:
Pub Dt:
05/18/2006
Title:
SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS
42
Patent #:
Issue Dt:
05/19/2015
Application #:
11162622
Filing Dt:
09/16/2005
Publication #:
Pub Dt:
08/03/2006
Title:
INTEGRATED, INTEGRATED CIRCUIT SINGULATION SYSTEM
43
Patent #:
Issue Dt:
11/29/2011
Application #:
11162629
Filing Dt:
09/16/2005
Publication #:
Pub Dt:
03/22/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECTS
44
Patent #:
Issue Dt:
01/03/2012
Application #:
11162635
Filing Dt:
09/16/2005
Publication #:
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM USING INTERPOSER
45
Patent #:
Issue Dt:
09/18/2007
Application #:
11162637
Filing Dt:
09/16/2005
Publication #:
Pub Dt:
08/24/2006
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
46
Patent #:
Issue Dt:
09/25/2007
Application #:
11162682
Filing Dt:
09/19/2005
Publication #:
Pub Dt:
03/22/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE RESTRAINT
47
Patent #:
Issue Dt:
06/28/2011
Application #:
11162785
Filing Dt:
09/22/2005
Publication #:
Pub Dt:
03/22/2007
Title:
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM
48
Patent #:
Issue Dt:
07/28/2009
Application #:
11162822
Filing Dt:
09/23/2005
Publication #:
Pub Dt:
03/29/2007
Title:
INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM
49
Patent #:
NONE
Issue Dt:
Application #:
11162828
Filing Dt:
09/24/2005
Publication #:
Pub Dt:
05/18/2006
Title:
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
50
Patent #:
NONE
Issue Dt:
Application #:
11162971
Filing Dt:
09/29/2005
Publication #:
Pub Dt:
03/29/2007
Title:
SUBSTRATE INDEXING SYSTEM
51
Patent #:
Issue Dt:
09/17/2013
Application #:
11163035
Filing Dt:
10/03/2005
Publication #:
Pub Dt:
04/05/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-SURFACE DIE ATTACH PAD
52
Patent #:
Issue Dt:
11/26/2013
Application #:
11163116
Filing Dt:
10/05/2005
Publication #:
Pub Dt:
04/05/2007
Title:
ULTRA-THIN WAFER SYSTEM AND METHOD OF MANUFACTURE THEREOF
53
Patent #:
Issue Dt:
12/18/2012
Application #:
11163156
Filing Dt:
10/07/2005
Publication #:
Pub Dt:
04/12/2007
Title:
WAFER LEVEL LASER MARKING SYSTEM FOR ULTRA-THIN WAFERS USING SUPPORT TAPE
54
Patent #:
Issue Dt:
04/24/2012
Application #:
11163305
Filing Dt:
10/13/2005
Publication #:
Pub Dt:
04/19/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM USING ETCHED LEADFRAME
55
Patent #:
NONE
Issue Dt:
Application #:
11163313
Filing Dt:
10/13/2005
Publication #:
Pub Dt:
04/19/2007
Title:
STACKED DIE PACKAGING SYSTEM
56
Patent #:
NONE
Issue Dt:
Application #:
11163547
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
04/26/2007
Title:
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
57
Patent #:
NONE
Issue Dt:
Application #:
11163556
Filing Dt:
10/22/2005
Publication #:
Pub Dt:
08/10/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED INTERLOCKING LEADFRAME
58
Patent #:
Issue Dt:
05/24/2011
Application #:
11163558
Filing Dt:
10/22/2005
Publication #:
Pub Dt:
04/26/2007
Title:
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS
59
Patent #:
Issue Dt:
04/14/2009
Application #:
11163559
Filing Dt:
10/22/2005
Publication #:
Pub Dt:
05/18/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
60
Patent #:
Issue Dt:
01/12/2010
Application #:
11163561
Filing Dt:
10/23/2005
Publication #:
Pub Dt:
05/18/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME SUBSTRATE
61
Patent #:
Issue Dt:
06/17/2008
Application #:
11163770
Filing Dt:
10/29/2005
Publication #:
Pub Dt:
08/24/2006
Title:
PACKAGE STACKING LEAD FRAME SYSTEM
62
Patent #:
Issue Dt:
11/24/2009
Application #:
11163771
Filing Dt:
10/29/2005
Publication #:
Pub Dt:
05/03/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HIGH-DENSITY SMALL FOOTPRINT SYSTEM-IN-PACKAGE
63
Patent #:
Issue Dt:
10/28/2008
Application #:
11164087
Filing Dt:
11/09/2005
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING RIBBON BOND INTERCONNECT
64
Patent #:
Issue Dt:
01/10/2012
Application #:
11164088
Filing Dt:
11/10/2005
Publication #:
Pub Dt:
08/17/2006
Title:
METHOD OF MANUFACTURING NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING ETCHED DIFFERENTIAL HEIGHT LEAD STRUCTURES
65
Patent #:
Issue Dt:
02/28/2012
Application #:
11164132
Filing Dt:
11/10/2005
Publication #:
Pub Dt:
05/18/2006
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HEAT SINK
66
Patent #:
Issue Dt:
10/09/2007
Application #:
11164160
Filing Dt:
11/12/2005
Publication #:
Pub Dt:
08/17/2006
Title:
STACKED DIE PACKAGE SYSTEM
67
Patent #:
Issue Dt:
04/24/2012
Application #:
11164209
Filing Dt:
11/14/2005
Publication #:
Pub Dt:
06/22/2006
Title:
HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM COMPRISING HEAT SLUGS ON OPPOSITE SURFACES OF A SEMICONDUCTOR CHIP
68
Patent #:
Issue Dt:
09/02/2008
Application #:
11164321
Filing Dt:
11/17/2005
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATED CIRCUIT SUPPORT
69
Patent #:
Issue Dt:
12/01/2009
Application #:
11164329
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
03/16/2006
Title:
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
70
Patent #:
Issue Dt:
12/01/2009
Application #:
11164329
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
03/16/2006
Title:
INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
71
Patent #:
Issue Dt:
03/19/2013
Application #:
11164335
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
05/24/2007
Title:
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM
72
Patent #:
Issue Dt:
06/28/2011
Application #:
11164336
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
08/03/2006
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
73
Patent #:
Issue Dt:
10/06/2009
Application #:
11164453
Filing Dt:
11/22/2005
Publication #:
Pub Dt:
09/07/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
74
Patent #:
Issue Dt:
09/29/2009
Application #:
11169850
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
10/27/2005
Title:
SEMICONDUCTOR PACKAGE FOR A LARGE DIE
75
Patent #:
Issue Dt:
09/29/2009
Application #:
11169850
Filing Dt:
06/28/2005
Publication #:
Pub Dt:
10/27/2005
Title:
SEMICONDUCTOR PACKAGE FOR A LARGE DIE
76
Patent #:
Issue Dt:
05/15/2007
Application #:
11213058
Filing Dt:
08/26/2005
Publication #:
Pub Dt:
01/26/2006
Title:
METHOD FOR MANUFACTURING PLASTIC BALL GRID ARRAY PACKAGE WITH INTEGRAL HEATSINK
77
Patent #:
Issue Dt:
11/28/2006
Application #:
11215090
Filing Dt:
08/29/2005
Publication #:
Pub Dt:
03/02/2006
Title:
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE
78
Patent #:
Issue Dt:
05/27/2008
Application #:
11234528
Filing Dt:
09/22/2005
Publication #:
Pub Dt:
04/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
79
Patent #:
Issue Dt:
04/24/2007
Application #:
11252193
Filing Dt:
10/17/2005
Publication #:
Pub Dt:
04/20/2006
Title:
MULTICHIP LEADFRAME PACKAGE
80
Patent #:
Issue Dt:
08/14/2007
Application #:
11252990
Filing Dt:
10/18/2005
Publication #:
Pub Dt:
05/04/2006
Title:
METHOD FOR REDUCING SEMICONDUCTOR DIE WARPAGE
81
Patent #:
Issue Dt:
01/25/2011
Application #:
11255740
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
08/17/2006
Title:
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM
82
Patent #:
Issue Dt:
10/09/2007
Application #:
11257894
Filing Dt:
10/24/2005
Publication #:
Pub Dt:
08/10/2006
Title:
NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
83
Patent #:
Issue Dt:
11/18/2008
Application #:
11273635
Filing Dt:
11/14/2005
Publication #:
Pub Dt:
06/01/2006
Title:
WIRE BOND INTERCONNECTION
84
Patent #:
Issue Dt:
03/02/2010
Application #:
11274925
Filing Dt:
11/14/2005
Publication #:
Pub Dt:
08/31/2006
Title:
SEMICONDUCTOR PACKAGE HAVING DOUBLE LAYER LEADFRAME
85
Patent #:
Issue Dt:
05/10/2011
Application #:
11276611
Filing Dt:
03/07/2006
Publication #:
Pub Dt:
09/13/2007
Title:
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM WITH A THERMAL DISSIPATION STRUCTURE
86
Patent #:
Issue Dt:
08/20/2013
Application #:
11276645
Filing Dt:
03/08/2006
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT LEADED STACKED PACKAGE SYSTEM
87
Patent #:
Issue Dt:
07/26/2011
Application #:
11276646
Filing Dt:
03/08/2006
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
88
Patent #:
Issue Dt:
07/19/2011
Application #:
11276647
Filing Dt:
03/08/2006
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM
89
Patent #:
Issue Dt:
10/06/2009
Application #:
11276681
Filing Dt:
03/09/2006
Publication #:
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
90
Patent #:
Issue Dt:
09/27/2011
Application #:
11276682
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
09/13/2007
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH PASSIVE COMPONENTS
91
Patent #:
Issue Dt:
08/23/2011
Application #:
11276684
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
09/13/2007
Title:
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
92
Patent #:
Issue Dt:
03/20/2012
Application #:
11276716
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING INTERCONNECT STACK AND EXTERNAL INTERCONNECT
93
Patent #:
Issue Dt:
09/07/2010
Application #:
11276727
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
94
Patent #:
Issue Dt:
05/06/2008
Application #:
11276940
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
95
Patent #:
Issue Dt:
10/30/2007
Application #:
11276941
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
96
Patent #:
Issue Dt:
02/05/2013
Application #:
11276942
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
97
Patent #:
Issue Dt:
07/27/2010
Application #:
11276945
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
SYSTEM FOR REMOVAL OF AN INTEGRATED CIRCUIT FROM A MOUNT MATERIAL
98
Patent #:
Issue Dt:
03/10/2009
Application #:
11276946
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
99
Patent #:
NONE
Issue Dt:
Application #:
11276947
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
100
Patent #:
Issue Dt:
04/21/2009
Application #:
11276948
Filing Dt:
03/17/2006
Publication #:
Pub Dt:
09/20/2007
Title:
MULTICHIP PACKAGE SYSTEM
Assignors
1
Exec Dt:
08/06/2015
2
Exec Dt:
08/06/2015
Assignee
1
39TH FLOOR, CITIBANK TOWER, CITIBANK PLAZA, 3 GARDEN ROAD
ATTENTION: AGENCY AND TRUST
CENTRAL, HONG KONG
Correspondence name and address
LAWRENCE KASS
28 LIBERTY STREET
C/O LAWRENCE KASS
NEW YORK, NY 10005

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