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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036288/0748   Pages: 247
Recorded: 08/06/2015
Attorney Dkt #:70341.00400
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1836
Page 3 of 19
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1
Patent #:
7304859
Issue Dt:
12/04/2007
Application #:
11277973
Filing Dt:
03/30/2006
Publication #:
US20070236900
Pub Dt:
10/11/2007
Title:
CHIP CARRIER AND FABRICATION METHOD
2
Patent #:
7671463
Issue Dt:
03/02/2010
Application #:
11277991
Filing Dt:
03/30/2006
Publication #:
US20070235854
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH GROUND RING
3
Patent #:
NONE
Issue Dt:
Application #:
11278002
Filing Dt:
03/30/2006
Publication #:
US20070235878
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
4
Patent #:
8395254
Issue Dt:
03/12/2013
Application #:
11278008
Filing Dt:
03/30/2006
Publication #:
US20070235859
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEATSPREADER
5
Patent #:
7977579
Issue Dt:
07/12/2011
Application #:
11278070
Filing Dt:
03/30/2006
Publication #:
US20070235215
Pub Dt:
10/11/2007
Title:
MULTIPLE FLIP-CHIP INTEGRATED CIRCUIT PACKAGE SYSTEM
6
Patent #:
7521781
Issue Dt:
04/21/2009
Application #:
11278343
Filing Dt:
03/31/2006
Publication #:
US20070108589
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD CLAMP LINE CRITICAL AREA HAVING WIDENED CONDUCTIVE TRACES
7
Patent #:
7829986
Issue Dt:
11/09/2010
Application #:
11278411
Filing Dt:
04/01/2006
Publication #:
US20070235846
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NET SPACER
8
Patent #:
7863737
Issue Dt:
01/04/2011
Application #:
11278414
Filing Dt:
04/01/2006
Publication #:
US20070235869
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE BOND PATTERN
9
Patent #:
7710735
Issue Dt:
05/04/2010
Application #:
11278418
Filing Dt:
04/01/2006
Publication #:
US20070235216
Pub Dt:
10/11/2007
Title:
MULTICHIP PACKAGE SYSTEM
10
Patent #:
7763961
Issue Dt:
07/27/2010
Application #:
11278420
Filing Dt:
04/01/2006
Publication #:
US20070235879
Pub Dt:
10/11/2007
Title:
HYBRID STACKING PACKAGE SYSTEM
11
Patent #:
7443037
Issue Dt:
10/28/2008
Application #:
11278421
Filing Dt:
04/01/2006
Publication #:
US20070229107
Pub Dt:
10/04/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONNECTION PROTECTION
12
Patent #:
7851268
Issue Dt:
12/14/2010
Application #:
11279131
Filing Dt:
04/10/2006
Publication #:
US20070108596
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
13
Patent #:
NONE
Issue Dt:
Application #:
11279741
Filing Dt:
04/13/2006
Publication #:
US20070111376
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
14
Patent #:
8067823
Issue Dt:
11/29/2011
Application #:
11280971
Filing Dt:
11/15/2005
Publication #:
US20060192294
Pub Dt:
08/31/2006
Title:
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
15
Patent #:
7880313
Issue Dt:
02/01/2011
Application #:
11282293
Filing Dt:
11/17/2005
Publication #:
US20060192295
Pub Dt:
08/31/2006
Title:
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER
16
Patent #:
8124455
Issue Dt:
02/28/2012
Application #:
11306098
Filing Dt:
12/15/2005
Publication #:
US20060219351
Pub Dt:
10/05/2006
Title:
WAFER STRENGTH REINFORCEMENT SYSTEM FOR ULTRA THIN WAFER THINNING
17
Patent #:
7445962
Issue Dt:
11/04/2008
Application #:
11306148
Filing Dt:
12/16/2005
Publication #:
US20060197209
Pub Dt:
09/07/2006
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH DENSE ROUTABILITY AND HIGH THERMAL CONDUCTIVITY
18
Patent #:
7443039
Issue Dt:
10/28/2008
Application #:
11306352
Filing Dt:
12/23/2005
Publication #:
US20060197223
Pub Dt:
09/07/2006
Title:
SYSTEM FOR DIFFERENT BOND PADS IN AN INTEGRATED CIRCUIT PACKAGE
19
Patent #:
7960816
Issue Dt:
06/14/2011
Application #:
11306354
Filing Dt:
12/23/2005
Publication #:
US20060197198
Pub Dt:
09/07/2006
Title:
SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
20
Patent #:
7456088
Issue Dt:
11/25/2008
Application #:
11306627
Filing Dt:
01/04/2006
Publication #:
US20070158833
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE
21
Patent #:
7364945
Issue Dt:
04/29/2008
Application #:
11306628
Filing Dt:
01/04/2006
Publication #:
US20060220256
Pub Dt:
10/05/2006
Title:
METHOD OF MOUNTING AN INTEGRATED CIRCUIT PACKAGE IN AN ENCAPSULANT CAVITY
22
Patent #:
7365417
Issue Dt:
04/29/2008
Application #:
11306693
Filing Dt:
01/06/2006
Publication #:
US20070158792
Pub Dt:
07/12/2007
Title:
OVERHANG INTEGRATED CIRCUIT PACKAGE SYSTEM
23
Patent #:
7446396
Issue Dt:
11/04/2008
Application #:
11306805
Filing Dt:
01/11/2006
Publication #:
US20070108604
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
24
Patent #:
8124459
Issue Dt:
02/28/2012
Application #:
11306806
Filing Dt:
01/11/2006
Publication #:
US20070108605
Pub Dt:
05/17/2007
Title:
BUMP CHIP CARRIER SEMICONDUCTOR PACKAGE SYSTEM
25
Patent #:
7323774
Issue Dt:
01/29/2008
Application #:
11306808
Filing Dt:
01/11/2006
Publication #:
US20070158820
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PEDESTAL STRUCTURE
26
Patent #:
7737539
Issue Dt:
06/15/2010
Application #:
11306854
Filing Dt:
01/12/2006
Publication #:
US20070158806
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
27
Patent #:
8120149
Issue Dt:
02/21/2012
Application #:
11307128
Filing Dt:
01/24/2006
Publication #:
US20070170559
Pub Dt:
07/26/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
28
Patent #:
8698294
Issue Dt:
04/15/2014
Application #:
11307129
Filing Dt:
01/24/2006
Publication #:
US20070170570
Pub Dt:
07/26/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WIDE FLANGE LEADFRAME
29
Patent #:
7598600
Issue Dt:
10/06/2009
Application #:
11307247
Filing Dt:
01/27/2006
Publication #:
US20070108560
Pub Dt:
05/17/2007
Title:
STACKABLE POWER SEMICONDUCTOR PACKAGE SYSTEM
30
Patent #:
7557432
Issue Dt:
07/07/2009
Application #:
11307285
Filing Dt:
01/31/2006
Publication #:
US20070108564
Pub Dt:
05/17/2007
Title:
THERMALLY ENHANCED POWER SEMICONDUCTOR PACKAGE SYSTEM
31
Patent #:
7615851
Issue Dt:
11/10/2009
Application #:
11307313
Filing Dt:
01/31/2006
Publication #:
US20070111394
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
32
Patent #:
7298052
Issue Dt:
11/20/2007
Application #:
11307314
Filing Dt:
01/31/2006
Publication #:
US20070111389
Pub Dt:
05/17/2007
Title:
MICRO CHIP-SCALE-PACKAGE SYSTEM
33
Patent #:
7485502
Issue Dt:
02/03/2009
Application #:
11307315
Filing Dt:
01/31/2006
Publication #:
US20070176285
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
34
Patent #:
NONE
Issue Dt:
Application #:
11307317
Filing Dt:
01/31/2006
Publication #:
US20070178666
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
35
Patent #:
NONE
Issue Dt:
Application #:
11307349
Filing Dt:
02/01/2006
Publication #:
US20070176271
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
36
Patent #:
7309622
Issue Dt:
12/18/2007
Application #:
11307350
Filing Dt:
02/01/2006
Publication #:
US20070111397
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
37
Patent #:
7414310
Issue Dt:
08/19/2008
Application #:
11307363
Filing Dt:
02/02/2006
Publication #:
US20070176280
Pub Dt:
08/02/2007
Title:
WAFERSCALE PACKAGE SYSTEM
38
Patent #:
8810018
Issue Dt:
08/19/2014
Application #:
11307382
Filing Dt:
02/03/2006
Publication #:
US20070181998
Pub Dt:
08/09/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FACE TO FACE STACK CONFIGURATION
39
Patent #:
7947534
Issue Dt:
05/24/2011
Application #:
11307383
Filing Dt:
02/04/2006
Publication #:
US20070182024
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING A NON-LEADED PACKAGE
40
Patent #:
7250685
Issue Dt:
07/31/2007
Application #:
11307384
Filing Dt:
02/04/2006
Publication #:
US20070108565
Pub Dt:
05/17/2007
Title:
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
41
Patent #:
7541221
Issue Dt:
06/02/2009
Application #:
11307386
Filing Dt:
02/04/2006
Publication #:
US20070181982
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT
42
Patent #:
7750482
Issue Dt:
07/06/2010
Application #:
11307482
Filing Dt:
02/09/2006
Publication #:
US20070182018
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING ZERO FILLET RESIN
43
Patent #:
NONE
Issue Dt:
Application #:
11307498
Filing Dt:
02/09/2006
Publication #:
US20070109756
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
44
Patent #:
8030755
Issue Dt:
10/04/2011
Application #:
11307532
Filing Dt:
02/10/2006
Publication #:
US20070108587
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH A HEAT SINK
45
Patent #:
7714451
Issue Dt:
05/11/2010
Application #:
11307614
Filing Dt:
02/14/2006
Publication #:
US20070108590
Pub Dt:
05/17/2007
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING
46
Patent #:
7435619
Issue Dt:
10/14/2008
Application #:
11307615
Filing Dt:
02/14/2006
Publication #:
US20070187826
Pub Dt:
08/16/2007
Title:
METHOD OF FABRICATING A 3-D PACKAGE STACKING SYSTEM
47
Patent #:
7400049
Issue Dt:
07/15/2008
Application #:
11307683
Filing Dt:
02/16/2006
Publication #:
US20070187839
Pub Dt:
08/16/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
48
Patent #:
7298037
Issue Dt:
11/20/2007
Application #:
11307722
Filing Dt:
02/17/2006
Publication #:
US20070194423
Pub Dt:
08/23/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH RECESSED SPACER
49
Patent #:
8120156
Issue Dt:
02/21/2012
Application #:
11307723
Filing Dt:
02/17/2006
Publication #:
US20070194424
Pub Dt:
08/23/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE ON BASE PACKAGE
50
Patent #:
7298038
Issue Dt:
11/20/2007
Application #:
11307861
Filing Dt:
02/25/2006
Publication #:
US20070200205
Pub Dt:
08/30/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
51
Patent #:
7385299
Issue Dt:
06/10/2008
Application #:
11307862
Filing Dt:
02/25/2006
Publication #:
US20070200257
Pub Dt:
08/30/2007
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE
52
Patent #:
8803299
Issue Dt:
08/12/2014
Application #:
11307904
Filing Dt:
02/27/2006
Publication #:
US20070200248
Pub Dt:
08/30/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
53
Patent #:
7741707
Issue Dt:
06/22/2010
Application #:
11307906
Filing Dt:
02/27/2006
Publication #:
US20070200230
Pub Dt:
08/30/2007
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
54
Patent #:
7723146
Issue Dt:
05/25/2010
Application #:
11326206
Filing Dt:
01/04/2006
Publication #:
US20070166867
Pub Dt:
07/19/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
55
Patent #:
7768125
Issue Dt:
08/03/2010
Application #:
11326211
Filing Dt:
01/04/2006
Publication #:
US20070158809
Pub Dt:
07/12/2007
Title:
MULTI-CHIP PACKAGE SYSTEM
56
Patent #:
8410594
Issue Dt:
04/02/2013
Application #:
11330930
Filing Dt:
01/11/2006
Publication #:
US20070158858
Pub Dt:
07/12/2007
Title:
INTER-STACKING MODULE SYSTEM
57
Patent #:
7312519
Issue Dt:
12/25/2007
Application #:
11331564
Filing Dt:
01/12/2006
Publication #:
US20070158810
Pub Dt:
07/12/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
58
Patent #:
NONE
Issue Dt:
Application #:
11337168
Filing Dt:
01/20/2006
Publication #:
US20060138649
Pub Dt:
06/29/2006
Title:
Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
59
Patent #:
7288434
Issue Dt:
10/30/2007
Application #:
11337821
Filing Dt:
01/23/2006
Publication #:
US20060141668
Pub Dt:
06/29/2006
Title:
METHOD FOR MAKING SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE AND INCLUDING ADDITIONAL DIE OR PACKAGE STACKED ON SECOND PACKAGE
60
Patent #:
7247519
Issue Dt:
07/24/2007
Application #:
11337944
Filing Dt:
01/23/2006
Publication #:
US20060158295
Pub Dt:
07/20/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED BUMP CHIP CARRIER SECOND PACKAGE
61
Patent #:
7449369
Issue Dt:
11/11/2008
Application #:
11338328
Filing Dt:
01/23/2006
Publication #:
US20070170554
Pub Dt:
07/26/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
62
Patent #:
8629537
Issue Dt:
01/14/2014
Application #:
11339176
Filing Dt:
01/23/2006
Publication #:
US20070170555
Pub Dt:
07/26/2007
Title:
PADLESS DIE SUPPORT INTEGRATED CIRCUIT PACKAGE SYSTEM
63
Patent #:
7521780
Issue Dt:
04/21/2009
Application #:
11354694
Filing Dt:
02/14/2006
Publication #:
US20070108597
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT DISSIPATION ENCLOSURE
64
Patent #:
8704349
Issue Dt:
04/22/2014
Application #:
11354806
Filing Dt:
02/14/2006
Publication #:
US20070190690
Pub Dt:
08/16/2007
Title:
Integrated circuit package system with exposed interconnects
65
Patent #:
7306973
Issue Dt:
12/11/2007
Application #:
11355920
Filing Dt:
02/16/2006
Publication #:
US20060151867
Pub Dt:
07/13/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING A PROCESSOR AND MEMORY PACKAGE ASSEMBLIES
66
Patent #:
7372170
Issue Dt:
05/13/2008
Application #:
11372755
Filing Dt:
03/10/2006
Publication #:
US20060170093
Pub Dt:
08/03/2006
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
67
Patent #:
7166494
Issue Dt:
01/23/2007
Application #:
11372988
Filing Dt:
03/10/2006
Publication #:
US20060172461
Pub Dt:
08/03/2006
Title:
METHOD OF FABRICATING A SEMICONDUCTOR STACKED MULIT-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE
68
Patent #:
7605480
Issue Dt:
10/20/2009
Application #:
11372989
Filing Dt:
03/10/2006
Publication #:
US20060163715
Pub Dt:
07/27/2006
Title:
FLIP CHIP INTERCONNECTION PAD LAYOUT
69
Patent #:
7420263
Issue Dt:
09/02/2008
Application #:
11374377
Filing Dt:
03/13/2006
Publication #:
US20060189101
Pub Dt:
08/24/2006
Title:
DBG SYSTEM AND METHOD WITH ADHESIVE LAYER SEVERING
70
Patent #:
7169642
Issue Dt:
01/30/2007
Application #:
11374378
Filing Dt:
03/13/2006
Publication #:
US20060172462
Pub Dt:
08/03/2006
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED LAND GRID ARRAY (LGA) PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
71
Patent #:
7163842
Issue Dt:
01/16/2007
Application #:
11374383
Filing Dt:
03/13/2006
Publication #:
US20060172459
Pub Dt:
08/03/2006
Title:
METHOD OF FABRICATING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING INVERTED SECOND PACKAGE STACKED OVER DIE-UP FLIP-CHIP BALL GRID ARRAY (BGA)
72
Patent #:
7279361
Issue Dt:
10/09/2007
Application #:
11374468
Filing Dt:
03/13/2006
Publication #:
US20060172463
Pub Dt:
08/03/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
73
Patent #:
7682873
Issue Dt:
03/23/2010
Application #:
11374472
Filing Dt:
03/13/2006
Publication #:
US20060170091
Pub Dt:
08/03/2006
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-DOWN FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
74
Patent #:
7975377
Issue Dt:
07/12/2011
Application #:
11379011
Filing Dt:
04/17/2006
Publication #:
US20070109749
Pub Dt:
05/17/2007
Title:
WAFER SCALE HEAT SLUG SYSTEM
75
Patent #:
NONE
Issue Dt:
Application #:
11379018
Filing Dt:
04/17/2006
Publication #:
US20070241441
Pub Dt:
10/18/2007
Title:
MULTICHIP PACKAGE SYSTEM
76
Patent #:
7420269
Issue Dt:
09/02/2008
Application #:
11379097
Filing Dt:
04/18/2006
Publication #:
US20070241442
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
77
Patent #:
7420269
Issue Dt:
09/02/2008
Application #:
11379097
Filing Dt:
04/18/2006
Publication #:
US20070241442
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
78
Patent #:
7498667
Issue Dt:
03/03/2009
Application #:
11379106
Filing Dt:
04/18/2006
Publication #:
US20070241453
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
79
Patent #:
7859098
Issue Dt:
12/28/2010
Application #:
11379332
Filing Dt:
04/19/2006
Publication #:
US20070246806
Pub Dt:
10/25/2007
Title:
EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM
80
Patent #:
8546929
Issue Dt:
10/01/2013
Application #:
11379336
Filing Dt:
04/19/2006
Publication #:
US20070246813
Pub Dt:
10/25/2007
Title:
EMBEDDED INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM
81
Patent #:
7339258
Issue Dt:
03/04/2008
Application #:
11379740
Filing Dt:
04/21/2006
Publication #:
US20060186515
Pub Dt:
08/24/2006
Title:
DUAL ROW LEADFRAME AND FABRICATION METHOD
82
Patent #:
7339258
Issue Dt:
03/04/2008
Application #:
11379740
Filing Dt:
04/21/2006
Publication #:
US20060186515
Pub Dt:
08/24/2006
Title:
DUAL ROW LEADFRAME AND FABRICATION METHOD
83
Patent #:
NONE
Issue Dt:
Application #:
11380587
Filing Dt:
04/27/2006
Publication #:
US20070109750
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
84
Patent #:
7354800
Issue Dt:
04/08/2008
Application #:
11380596
Filing Dt:
04/27/2006
Publication #:
US20060244157
Pub Dt:
11/02/2006
Title:
METHOD OF FABRICATING A STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
85
Patent #:
8009436
Issue Dt:
08/30/2011
Application #:
11380652
Filing Dt:
04/27/2006
Publication #:
US20070109757
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHANNEL
86
Patent #:
7763963
Issue Dt:
07/27/2010
Application #:
11381683
Filing Dt:
05/04/2006
Publication #:
US20060249828
Pub Dt:
11/09/2006
Title:
STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
87
Patent #:
8138586
Issue Dt:
03/20/2012
Application #:
11381684
Filing Dt:
05/04/2006
Publication #:
US20070108566
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-PLANAR PADDLE
88
Patent #:
7498665
Issue Dt:
03/03/2009
Application #:
11381726
Filing Dt:
05/04/2006
Publication #:
US20070108567
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
89
Patent #:
7443015
Issue Dt:
10/28/2008
Application #:
11381734
Filing Dt:
05/04/2006
Publication #:
US20070108624
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
90
Patent #:
7495325
Issue Dt:
02/24/2009
Application #:
11381827
Filing Dt:
05/05/2006
Publication #:
US20060266938
Pub Dt:
11/30/2006
Title:
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
91
Patent #:
7582960
Issue Dt:
09/01/2009
Application #:
11381901
Filing Dt:
05/05/2006
Publication #:
US20060249851
Pub Dt:
11/09/2006
Title:
MULTIPLE CHIP PACKAGE MODULE INCLUDING DIE STACKED OVER ENCAPSULATED PACKAGE
92
Patent #:
8395251
Issue Dt:
03/12/2013
Application #:
11382983
Filing Dt:
05/12/2006
Publication #:
US20070108568
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE TO PACKAGE STACKING SYSTEM
93
Patent #:
7482683
Issue Dt:
01/27/2009
Application #:
11383038
Filing Dt:
05/12/2006
Publication #:
US20070262423
Pub Dt:
11/15/2007
Title:
INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
94
Patent #:
7518224
Issue Dt:
04/14/2009
Application #:
11383403
Filing Dt:
05/15/2006
Publication #:
US20070108581
Pub Dt:
05/17/2007
Title:
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
95
Patent #:
7746656
Issue Dt:
06/29/2010
Application #:
11383407
Filing Dt:
05/15/2006
Publication #:
US20060256525
Pub Dt:
11/16/2006
Title:
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
96
Patent #:
NONE
Issue Dt:
Application #:
11383802
Filing Dt:
05/17/2006
Publication #:
US20070268660
Pub Dt:
11/22/2007
Title:
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
97
Patent #:
NONE
Issue Dt:
Application #:
11388755
Filing Dt:
03/24/2006
Publication #:
US20060216860
Pub Dt:
09/28/2006
Title:
Flip chip interconnection having narrow interconnection sites on the substrate
98
Patent #:
7545031
Issue Dt:
06/09/2009
Application #:
11394363
Filing Dt:
03/30/2006
Publication #:
US20060226528
Pub Dt:
10/12/2006
Title:
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
99
Patent #:
7429786
Issue Dt:
09/30/2008
Application #:
11394635
Filing Dt:
03/31/2006
Publication #:
US20060244117
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR PACKAGE INCLUDING SECOND SUBSTRATE AND HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
100
Patent #:
7372141
Issue Dt:
05/13/2008
Application #:
11395529
Filing Dt:
03/31/2006
Publication #:
US20060220209
Pub Dt:
10/05/2006
Title:
SEMICONDUCTOR STACKED PACKAGE ASSEMBLY HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
Assignors
1
STATS CHIPPAC, INC.
Exec Dt:
08/06/2015
2
STATS CHIPPAC LTD.
Exec Dt:
08/06/2015
Assignee
1
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
39TH FLOOR, CITIBANK TOWER, CITIBANK PLAZA, 3 GARDEN ROAD
ATTENTION: AGENCY AND TRUST
CENTRAL, HONG KONG
Correspondence name and address
LAWRENCE KASS
28 LIBERTY STREET
C/O LAWRENCE KASS
NEW YORK, NY 10005

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