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Reel/Frame:	049669/0749			Pages:	21
		Recorded:	07/02/2019
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 323
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Patent #:	9460924	Issue Dt:	10/04/2016	Application #:	11691332	Filing Dt:	03/26/2007
Publication #:	US20080237803	Pub Dt:	10/02/2008
Title:	SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM

Patent #:	9640666	Issue Dt:	05/02/2017	Application #:	11781664	Filing Dt:	07/23/2007
Publication #:	US20090026545	Pub Dt:	01/29/2009
Title:	INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM

Patent #:	9218994	Issue Dt:	12/22/2015	Application #:	12039980	Filing Dt:	02/29/2008
Publication #:	US20090035101	Pub Dt:	02/05/2009
Title:	TWO-DIMENSIONAL TRANSFER STATION USED AS INTERFACE BETWEEN A PROCESS TOOL AND A TRANSPORT SYSTEM AND A METHOD OF OPERATING THE SAME

Patent #:	9393633	Issue Dt:	07/19/2016	Application #:	12551960	Filing Dt:	09/01/2009
Publication #:	US20110049221	Pub Dt:	03/03/2011
Title:	METHOD OF JOINING A CHIP ON A SUBSTRATE

Patent #:	9331174	Issue Dt:	05/03/2016	Application #:	12760688	Filing Dt:	04/15/2010
Publication #:	US20110254015	Pub Dt:	10/20/2011
Title:	METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe)

Patent #:	9461169	Issue Dt:	10/04/2016	Application #:	12789792	Filing Dt:	05/28/2010
Publication #:	US20110291100	Pub Dt:	12/01/2011
Title:	DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER

Patent #:	9449822	Issue Dt:	09/20/2016	Application #:	12846020	Filing Dt:	07/29/2010
Publication #:	US20120028476	Pub Dt:	02/02/2012
Title:	METHOD OF FORMING SEMICONDUCTOR STRUCTURES WITH CONTACT HOLES

Patent #:	9234291	Issue Dt:	01/12/2016	Application #:	12878787	Filing Dt:	09/09/2010
Publication #:	US20120061250	Pub Dt:	03/15/2012
Title:	Zinc Thin Films Plating Chemistry and Methods

Patent #:	9406562	Issue Dt:	08/02/2016	Application #:	13005883	Filing Dt:	01/13/2011
Publication #:	US20120181700	Pub Dt:	07/19/2012
Title:	INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS

Patent #:	9269634	Issue Dt:	02/23/2016	Application #:	13108138	Filing Dt:	05/16/2011
Publication #:	US20120292710	Pub Dt:	11/22/2012
Title:	SELF-ALIGNED METAL GATE CMOS WITH METAL BASE LAYER AND DUMMY GATE STRUCTURE

Patent #:	9281200	Issue Dt:	03/08/2016	Application #:	13189997	Filing Dt:	07/25/2011
Publication #:	US20120156865	Pub Dt:	06/21/2012
Title:	ENHANCED PATTERNING UNIFORMITY OF GATE ELECTRODES OF A SEMICONDUCTOR DEVICE BY LATE GATE DOPING

Patent #:	9318345	Issue Dt:	04/19/2016	Application #:	13253210	Filing Dt:	10/05/2011
Publication #:	US20130089985	Pub Dt:	04/11/2013
Title:	Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach

Patent #:	9620619	Issue Dt:	04/11/2017	Application #:	13348894	Filing Dt:	01/12/2012
Publication #:	US20130181261	Pub Dt:	07/18/2013
Title:	BORDERLESS CONTACT STRUCTURE

Patent #:	9548378	Issue Dt:	01/17/2017	Application #:	13369856	Filing Dt:	02/09/2012
Publication #:	US20130210216	Pub Dt:	08/15/2013
Title:	EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES

Patent #:	9396977	Issue Dt:	07/19/2016	Application #:	13414875	Filing Dt:	03/08/2012
Publication #:	US20130236274	Pub Dt:	09/12/2013
Title:	MOISTURE AND/OR ELECTRICALLY CONDUCTIVE REMAINS DETECTION FOR WAFERS AFTER RINSE / DRY PROCESS

Patent #:	9236314	Issue Dt:	01/12/2016	Application #:	13433659	Filing Dt:	03/29/2012
Publication #:	US20120184093	Pub Dt:	07/19/2012
Title:	HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS

Patent #:	9224604	Issue Dt:	12/29/2015	Application #:	13440546	Filing Dt:	04/05/2012
Publication #:	US20130264612	Pub Dt:	10/10/2013
Title:	DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP

Patent #:	9190471	Issue Dt:	11/17/2015	Application #:	13446350	Filing Dt:	04/13/2012
Publication #:	US20130270611	Pub Dt:	10/17/2013
Title:	SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS

Patent #:	9431295	Issue Dt:	08/30/2016	Application #:	13602496	Filing Dt:	09/04/2012
Publication #:	US20120325532	Pub Dt:	12/27/2012
Title:	INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME

Patent #:	9437677	Issue Dt:	09/06/2016	Application #:	13604739	Filing Dt:	09/06/2012
Publication #:	US20120326125	Pub Dt:	12/27/2012
Title:	Deposition On A Nanowire Using Atomic Layer Deposition

Patent #:	9287136	Issue Dt:	03/15/2016	Application #:	13606873	Filing Dt:	09/07/2012
Publication #:	US20130032865	Pub Dt:	02/07/2013
Title:	FINFET FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING

Patent #:	9607862	Issue Dt:	03/28/2017	Application #:	13610262	Filing Dt:	09/11/2012
Publication #:	US20140070401	Pub Dt:	03/13/2014
Title:	EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING

Patent #:	9273408	Issue Dt:	03/01/2016	Application #:	13612812	Filing Dt:	09/12/2012
Publication #:	US20140069817	Pub Dt:	03/13/2014
Title:	DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS

Patent #:	9245794	Issue Dt:	01/26/2016	Application #:	13614492	Filing Dt:	09/13/2012
Publication #:	US20130000962	Pub Dt:	01/03/2013
Title:	FORMATION OF ALLOY LINER BY REACTION OF DIFFUSION BARRIER AND SEED LAYER FOR INTERCONNECT APPLICATION

Patent #:	9177822	Issue Dt:	11/03/2015	Application #:	13615770	Filing Dt:	09/14/2012
Publication #:	US20130011936	Pub Dt:	01/10/2013
Title:	SELECTIVE ETCHING BATH METHODS

Patent #:	9196523	Issue Dt:	11/24/2015	Application #:	13616394	Filing Dt:	09/14/2012
Publication #:	US20130001801	Pub Dt:	01/03/2013
Title:	SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES

Patent #:	9275911	Issue Dt:	03/01/2016	Application #:	13650591	Filing Dt:	10/12/2012
Publication #:	US20140103450	Pub Dt:	04/17/2014
Title:	HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR

Patent #:	9412629	Issue Dt:	08/09/2016	Application #:	13658856	Filing Dt:	10/24/2012
Publication #:	US20140113433	Pub Dt:	04/24/2014
Title:	WAFER BONDING FOR 3D DEVICE PACKAGING FABRICATION

Patent #:	9240352	Issue Dt:	01/19/2016	Application #:	13659292	Filing Dt:	10/24/2012
Publication #:	US20140110767	Pub Dt:	04/24/2014
Title:	BULK FINFET WELL CONTACTS WITH FIN PATTERN UNIFORMITY

Patent #:	9190486	Issue Dt:	11/17/2015	Application #:	13682331	Filing Dt:	11/20/2012
Publication #:	US20140138779	Pub Dt:	05/22/2014
Title:	INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE

Patent #:	9299638	Issue Dt:	03/29/2016	Application #:	13707003	Filing Dt:	12/06/2012
Publication #:	US20140159227	Pub Dt:	06/12/2014
Title:	PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS

Patent #:	9558997	Issue Dt:	01/31/2017	Application #:	13729180	Filing Dt:	12/28/2012
Publication #:	US20140187036	Pub Dt:	07/03/2014
Title:	INTEGRATION OF Ru WET ETCH AND CMP FOR BEOL INTERCONNECTS WITH Ru LAYER

Patent #:	9285417	Issue Dt:	03/15/2016	Application #:	13732482	Filing Dt:	01/02/2013
Publication #:	US20140184262	Pub Dt:	07/03/2014
Title:	LOW-VOLTAGE IC TEST FOR DEFECT SCREENING

Patent #:	9312203	Issue Dt:	04/12/2016	Application #:	13732825	Filing Dt:	01/02/2013
Publication #:	US20140183739	Pub Dt:	07/03/2014
Title:	DUAL DAMASCENE STRUCTURE WITH LINER

Patent #:	9299639	Issue Dt:	03/29/2016	Application #:	13734524	Filing Dt:	01/04/2013
Publication #:	US20140159242	Pub Dt:	06/12/2014
Title:	PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS

Patent #:	9337082	Issue Dt:	05/10/2016	Application #:	13744756	Filing Dt:	01/18/2013
Publication #:	US20140203447	Pub Dt:	07/24/2014
Title:	METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT

Patent #:	9236271	Issue Dt:	01/12/2016	Application #:	13749330	Filing Dt:	01/24/2013
Publication #:	US20130280885	Pub Dt:	10/24/2013
Title:	LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING

Patent #:	9412640	Issue Dt:	08/09/2016	Application #:	13749830	Filing Dt:	01/25/2013
Publication #:	US20140213053	Pub Dt:	07/31/2014
Title:	SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD

Patent #:	9349635	Issue Dt:	05/24/2016	Application #:	13770464	Filing Dt:	02/19/2013
Publication #:	US20140232010	Pub Dt:	08/21/2014
Title:	INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTI-LEVEL ELECTRICAL CONNECTION

Patent #:	9356119	Issue Dt:	05/31/2016	Application #:	13770545	Filing Dt:	02/19/2013
Publication #:	US20130157423	Pub Dt:	06/20/2013
Title:	MOSFETs WITH REDUCED CONTACT RESISTANCE

Patent #:	9331141	Issue Dt:	05/03/2016	Application #:	13773014	Filing Dt:	02/21/2013
Publication #:	US20130221479	Pub Dt:	08/29/2013
Title:	CMOS STRUCTURE ON REPLACEMENT SUBSTRATE

Patent #:	9293461	Issue Dt:	03/22/2016	Application #:	13780003	Filing Dt:	02/28/2013
Publication #:	US20130175635	Pub Dt:	07/11/2013
Title:	REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL

Patent #:	9214397	Issue Dt:	12/15/2015	Application #:	13788689	Filing Dt:	03/07/2013
Publication #:	US20130316503	Pub Dt:	11/28/2013
Title:	STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs)

Patent #:	9196528	Issue Dt:	11/24/2015	Application #:	13798643	Filing Dt:	03/13/2013
Publication #:	US20130200434	Pub Dt:	08/08/2013
Title:	USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

Patent #:	9287109	Issue Dt:	03/15/2016	Application #:	13798764	Filing Dt:	03/13/2013
Publication #:	US20140264758	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING A PROTECTION LAYER TO PROTECT A METAL HARD MASK LAYER DURING LITHOGRAPHY REWORKING PROCESSES

Patent #:	9250623	Issue Dt:	02/02/2016	Application #:	13833932	Filing Dt:	03/15/2013
Publication #:	US20140277668	Pub Dt:	09/18/2014
Title:	METHODS AND SYSTEMS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING UNIVERSAL AND LOCAL PROCESSING MANAGEMENT

Patent #:	9406565	Issue Dt:	08/02/2016	Application #:	13842077	Filing Dt:	03/15/2013
Publication #:	US20140273375	Pub Dt:	09/18/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SEMICONDUCTOR SUBSTRATE PROTECTION

Patent #:	9337261	Issue Dt:	05/10/2016	Application #:	13859966	Filing Dt:	04/10/2013
Publication #:	US20150243732	Pub Dt:	08/27/2015
Title:	METHOD OF FORMING MICROELECTRONIC OR MICROMECHANICAL STRUCTURES

Patent #:	9530654	Issue Dt:	12/27/2016	Application #:	13862819	Filing Dt:	04/15/2013
Publication #:	US20140306317	Pub Dt:	10/16/2014
Title:	FINFET FIN HEIGHT CONTROL

Patent #:	9379007	Issue Dt:	06/28/2016	Application #:	13874509	Filing Dt:	05/01/2013
Publication #:	US20130252418	Pub Dt:	09/26/2013
Title:	ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES

Patent #:	9269603	Issue Dt:	02/23/2016	Application #:	13890776	Filing Dt:	05/09/2013
Publication #:	US20140332810	Pub Dt:	11/13/2014
Title:	TEMPORARY LIQUID THERMAL INTERFACE MATERIAL FOR SURFACE TENSION ADHESION AND THERMAL CONTROL

Patent #:	9231094	Issue Dt:	01/05/2016	Application #:	13898585	Filing Dt:	05/21/2013
Publication #:	US20140346567	Pub Dt:	11/27/2014
Title:	ELEMENTAL SEMICONDUCTOR MATERIAL CONTACTFOR HIGH ELECTRON MOBILITY TRANSISTOR

Patent #:	9281198	Issue Dt:	03/08/2016	Application #:	13900808	Filing Dt:	05/23/2013
Publication #:	US20140346573	Pub Dt:	11/27/2014
Title:	METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES

Patent #:	9171754	Issue Dt:	10/27/2015	Application #:	13901739	Filing Dt:	05/24/2013
Publication #:	US20140349478	Pub Dt:	11/27/2014
Title:	METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS

Patent #:	9305894	Issue Dt:	04/05/2016	Application #:	13910152	Filing Dt:	06/05/2013
Publication #:	US20140359995	Pub Dt:	12/11/2014
Title:	CONSTRAINED DIE ADHESION CURE PROCESS

Patent #:	9202911	Issue Dt:	12/01/2015	Application #:	13912448	Filing Dt:	06/07/2013
Publication #:	US20140361365	Pub Dt:	12/11/2014
Title:	SELF-ALIGNED CHANNEL DRIFT DEVICE AND METHODS OF MAKING SUCH A DEVICE

Patent #:	9190411	Issue Dt:	11/17/2015	Application #:	13914808	Filing Dt:	06/11/2013
Publication #:	US20140361377	Pub Dt:	12/11/2014
Title:	RETROGRADE DOPED LAYER FOR DEVICE ISOLATION

Patent #:	9646929	Issue Dt:	05/09/2017	Application #:	13916669	Filing Dt:	06/13/2013
Publication #:	US20140367826	Pub Dt:	12/18/2014
Title:	MAKING AN EFUSE

Patent #:	9385233	Issue Dt:	07/05/2016	Application #:	13927698	Filing Dt:	06/26/2013
Publication #:	US20150001591	Pub Dt:	01/01/2015
Title:	BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THROUGH STOPPING LAYER UNDER THE OXIDE

Patent #:	9224610	Issue Dt:	12/29/2015	Application #:	13931205	Filing Dt:	06/28/2013
Publication #:	US20150001643	Pub Dt:	01/01/2015
Title:	INTEGRATED CIRCUITS HAVING IMPROVED HIGH-K DIELECTRIC LAYERS AND METHODS FOR FABRICATION OF SAME

Patent #:	9275951	Issue Dt:	03/01/2016	Application #:	13945678	Filing Dt:	07/18/2013
Publication #:	US20130307158	Pub Dt:	11/21/2013
Title:	CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT

Patent #:	9209086	Issue Dt:	12/08/2015	Application #:	13947316	Filing Dt:	07/22/2013
Publication #:	US20150021715	Pub Dt:	01/22/2015
Title:	Low Temperature Salicide for Replacement Gate Nanowires

Patent #:	9209094	Issue Dt:	12/08/2015	Application #:	13952993	Filing Dt:	07/29/2013
Publication #:	US20150028419	Pub Dt:	01/29/2015
Title:	FIN FIELD EFFECT TRANSISTOR WITH DIELECTRIC ISOLATION AND ANCHORED STRESSOR ELEMENTS

Patent #:	9472554	Issue Dt:	10/18/2016	Application #:	13955693	Filing Dt:	07/31/2013
Publication #:	US20150034941	Pub Dt:	02/05/2015
Title:	INTEGRATED CIRCUITS HAVING FINFET SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME TO RESIST SUB-FIN CURRENT LEAKAGE

Patent #:	9418993	Issue Dt:	08/16/2016	Application #:	13958938	Filing Dt:	08/05/2013
Publication #:	US20150035053	Pub Dt:	02/05/2015
Title:	DEVICE AND METHOD FOR A LDMOS DESIGN FOR A FINFET INTEGRATED CIRCUIT

Patent #:	9373691	Issue Dt:	06/21/2016	Application #:	13961282	Filing Dt:	08/07/2013
Publication #:	US20150041824	Pub Dt:	02/12/2015
Title:	TRANSISTOR WITH BONDED GATE DIELECTRIC

Patent #:	9548238	Issue Dt:	01/17/2017	Application #:	13964286	Filing Dt:	08/12/2013
Publication #:	US20150044870	Pub Dt:	02/12/2015
Title:	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A SELF-ALIGNED OPL REPLACEMENT CONTACT AND PATTERNED HSQ AND A SEMICONDUCTOR DEVICE FORMED BY SAME

Patent #:	9177874	Issue Dt:	11/03/2015	Application #:	14012563	Filing Dt:	08/28/2013
Publication #:	US20150064812	Pub Dt:	03/05/2015
Title:	METHOD OF FORMING A SEMICONDUCTOR DEVICE EMPLOYING AN OPTICAL PLANARIZATION LAYER

Patent #:	9431264	Issue Dt:	08/30/2016	Application #:	14014906	Filing Dt:	08/30/2013
Publication #:	US20150064912	Pub Dt:	03/05/2015
Title:	METHODS OF FORMING INTEGRATED CIRCUITS AND MULTIPLE CRITICAL DIMENSION SELF-ALIGNED DOUBLE PATTERNING PROCESSES

Patent #:	9275874	Issue Dt:	03/01/2016	Application #:	14015640	Filing Dt:	08/30/2013
Publication #:	US20150064903	Pub Dt:	03/05/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL PLANARIZATION TO RECESS METAL

Patent #:	9472651	Issue Dt:	10/18/2016	Application #:	14017461	Filing Dt:	09/04/2013
Publication #:	US20150064854	Pub Dt:	03/05/2015
Title:	SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME

Patent #:	9224755	Issue Dt:	12/29/2015	Application #:	14020098	Filing Dt:	09/06/2013
Publication #:	US20150069333	Pub Dt:	03/12/2015
Title:	FLEXIBLE ACTIVE MATRIX DISPLAY

Patent #:	9224822	Issue Dt:	12/29/2015	Application #:	14023007	Filing Dt:	09/10/2013
Publication #:	US20150069465	Pub Dt:	03/12/2015
Title:	HIGH PERCENTAGE SILICON GERMANIUM ALLOY FIN FORMATION

Patent #:	9305879	Issue Dt:	04/05/2016	Application #:	14024694	Filing Dt:	09/12/2013
Publication #:	US20140332923	Pub Dt:	11/13/2014
Title:	E-FUSE WITH HYBRID METALLIZATION

Patent #:	9337313	Issue Dt:	05/10/2016	Application #:	14027331	Filing Dt:	09/16/2013
Publication #:	US20150061018	Pub Dt:	03/05/2015
Title:	SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME

Patent #:	9219002	Issue Dt:	12/22/2015	Application #:	14028724	Filing Dt:	09/17/2013
Publication #:	US20150076653	Pub Dt:	03/19/2015
Title:	OVERLAY PERFORMANCE FOR A FIN FIELD EFFECT TRANSISTOR DEVICE

Patent #:	9293632	Issue Dt:	03/22/2016	Application #:	14030019	Filing Dt:	09/18/2013
Publication #:	US20150079723	Pub Dt:	03/19/2015
Title:	Pressure Transfer Process for Thin Film Solar Cell Fabrication

Patent #:	9401263	Issue Dt:	07/26/2016	Application #:	14031563	Filing Dt:	09/19/2013
Publication #:	US20150076111	Pub Dt:	03/19/2015
Title:	FEATURE ETCHING USING VARYING SUPPLY OF POWER PULSES

Patent #:	9356114	Issue Dt:	05/31/2016	Application #:	14042951	Filing Dt:	10/01/2013
Publication #:	US20150093872	Pub Dt:	04/02/2015
Title:	LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR WITH LOW TEMPERATURE RECESSED CONTACTS

Patent #:	9196694	Issue Dt:	11/24/2015	Application #:	14043017	Filing Dt:	10/01/2013
Publication #:	US20150091093	Pub Dt:	04/02/2015
Title:	INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME

Patent #:	9275889	Issue Dt:	03/01/2016	Application #:	14045340	Filing Dt:	10/03/2013
Publication #:	US20150097263	Pub Dt:	04/09/2015
Title:	METHOD AND APPARATUS FOR HIGH YIELD CONTACT INTEGRATION SCHEME

Patent #:	9620381	Issue Dt:	04/11/2017	Application #:	14050472	Filing Dt:	10/10/2013
Publication #:	US20150104948	Pub Dt:	04/16/2015
Title:	FACILITATING ETCH PROCESSING OF A THIN FILM VIA PARTIAL IMPLANTATION THEREOF

Patent #:	9418902	Issue Dt:	08/16/2016	Application #:	14050661	Filing Dt:	10/10/2013
Publication #:	US20150102409	Pub Dt:	04/16/2015
Title:	FORMING ISOLATED FINS FROM A SUBSTRATE

Patent #:	9443764	Issue Dt:	09/13/2016	Application #:	14052366	Filing Dt:	10/11/2013
Publication #:	US20150101856	Pub Dt:	04/16/2015
Title:	METHOD OF ELIMINATING POOR REVEAL OF THROUGH SILICON VIAS

Patent #:	9263583	Issue Dt:	02/16/2016	Application #:	14052924	Filing Dt:	10/14/2013
Publication #:	US20150102348	Pub Dt:	04/16/2015
Title:	INTEGRATED FINFET-BJT REPLACEMENT METAL GATE

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100

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Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/26/2018

Assignee

ALSEPHINA INNOVATIONS INC.

303 TERRY FOX DRIVE

SUITE 300

OTTAWA, CANADA K2K 3J1

Correspondence name and address
	ALSEPHINA INNOVATIONS INC.
	1891 ROBERTSON ROAD
	SUITE 100
	OTTAWA, K2H 5B7 CANADA

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