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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	044886/0766			Pages:	67
		Recorded:	12/17/2017
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 524
Page 4 of 6
Pages: 1 2 3 4 5 6

Patent #:	6678950	Issue Dt:	01/20/2004	Application #:	10007247	Filing Dt:	11/01/2001
Title:	A METHOD FOR FORMING A BONDING PAD ON A SUBSTRATE

Patent #:	7009299	Issue Dt:	03/07/2006	Application #:	10021174	Filing Dt:	10/29/2001
Publication #:	US20020045330	Pub Dt:	04/18/2002
Title:	KINETICALLY CONTROLLED SOLDER

Patent #:	6573523	Issue Dt:	06/03/2003	Application #:	10021829	Filing Dt:	12/12/2001
Title:	SUBSTRATE SURFACE SCANNING

Patent #:	6590409	Issue Dt:	07/08/2003	Application #:	10023311	Filing Dt:	12/13/2001
Title:	SYSTEMS AND METHODS FOR PACKAGE DEFECT DETECTION

Patent #:	6769923	Issue Dt:	08/03/2004	Application #:	10024054	Filing Dt:	12/17/2001
Publication #:	US20030114026	Pub Dt:	06/19/2003
Title:	FLUTED SIGNAL PIN, CAP, MEMBRANE, AND STANCHION FOR A BALL GRID ARRAY

Patent #:	6605954	Issue Dt:	08/12/2003	Application #:	10055812	Filing Dt:	01/23/2002
Title:	REDUCING PROBE CARD SUBSTRATE WARPAGE

Patent #:	6617181	Issue Dt:	09/09/2003	Application #:	10061518	Filing Dt:	02/01/2002
Title:	FLIP CHIP TESTING

Patent #:	6674176	Issue Dt:	01/06/2004	Application #:	10082027	Filing Dt:	02/20/2002
Publication #:	US20030155633	Pub Dt:	08/21/2003
Title:	WIRE BOND PACKAGE WITH CORE RING FORMED OVER I/O CELLS

Patent #:	6727567	Issue Dt:	04/27/2004	Application #:	10091291	Filing Dt:	03/05/2002
Publication #:	US20020092462	Pub Dt:	07/18/2002
Title:	INTEGRATED CIRCUIT DEVICE SUBSTRATES WITH SELECTIVE EPITAXIAL GROWTH THICKNESS COMPENSATION

Patent #:	6623992	Issue Dt:	09/23/2003	Application #:	10094549	Filing Dt:	03/08/2002
Title:	SYSTEM AND METHOD FOR DETERMINING A SUBTHRESHOLD LEAKAGE TEST LIMIT OF AN INTEGRATED CIRCUIT

Patent #:	6847123	Issue Dt:	01/25/2005	Application #:	10114144	Filing Dt:	04/02/2002
Publication #:	US20030183953	Pub Dt:	10/02/2003
Title:	VERTICALLY STAGGERED BONDPAD ARRAY

Patent #:	6815812	Issue Dt:	11/09/2004	Application #:	10141252	Filing Dt:	05/08/2002
Publication #:	US20030209797	Pub Dt:	11/13/2003
Title:	DIRECT ALIGNMENT OF CONTACTS

Patent #:	6628001	Issue Dt:	09/30/2003	Application #:	10150790	Filing Dt:	05/17/2002
Title:	INTEGRATED CIRCUIT DIE HAVING ALIGNMENT MARKS IN THE BOND PAD REGION AND METHOD OF MANUFACTURING SAME

Patent #:	6777314	Issue Dt:	08/17/2004	Application #:	10211914	Filing Dt:	08/02/2002
Publication #:	US20040023481	Pub Dt:	02/05/2004
Title:	METHOD OF FORMING ELECTROLYTIC CONTACT PADS INCLUDING LAYERS OF COPPER, NICKEL, AND GOLD

Patent #:	6700207	Issue Dt:	03/02/2004	Application #:	10212448	Filing Dt:	08/05/2002
Publication #:	US20040021232	Pub Dt:	02/05/2004
Title:	FLIP-CHIP BALL GRID ARRAY PACKAGE FOR ELECTROMIGRATION TESTING

Patent #:	6833286	Issue Dt:	12/21/2004	Application #:	10218783	Filing Dt:	08/14/2002
Publication #:	US20020190347	Pub Dt:	12/19/2002
Title:	SEMICONDUCTOR DEVICE WITH VARIABLE PIN LOCATIONS

Patent #:	6781150	Issue Dt:	08/24/2004	Application #:	10229601	Filing Dt:	08/28/2002
Publication #:	US20040043656	Pub Dt:	03/04/2004
Title:	TEST STRUCTURE

Patent #:	6777803	Issue Dt:	08/17/2004	Application #:	10229659	Filing Dt:	08/28/2002
Publication #:	US20040041252	Pub Dt:	03/04/2004
Title:	SOLDER MASK ON BONDING RING

Patent #:	6849936	Issue Dt:	02/01/2005	Application #:	10254473	Filing Dt:	09/25/2002
Title:	SYSTEM AND METHOD FOR USING FILM DEPOSITION TECHNIQUES TO PROVIDE AN ANTENNA WITHIN AN INTEGRATED CIRCUIT PACKAGE

Patent #:	6680532	Issue Dt:	01/20/2004	Application #:	10265751	Filing Dt:	10/07/2002
Title:	MULTI CHIP MODULE

Patent #:	6881613	Issue Dt:	04/19/2005	Application #:	10266267	Filing Dt:	10/08/2002
Publication #:	US20040065950	Pub Dt:	04/08/2004
Title:	ELECTRONIC COMPONENT PACKAGE

Patent #:	6861343	Issue Dt:	03/01/2005	Application #:	10267410	Filing Dt:	10/09/2002
Publication #:	US20040072414	Pub Dt:	04/15/2004
Title:	BUFFER METAL LAYER

Patent #:	6717423	Issue Dt:	04/06/2004	Application #:	10267814	Filing Dt:	10/09/2002
Publication #:	US20040070402	Pub Dt:	04/15/2004
Title:	SUBSTRATE IMPEDANCE MEASUREMENT

Patent #:	7041516	Issue Dt:	05/09/2006	Application #:	10268361	Filing Dt:	10/10/2002
Publication #:	US20040072377	Pub Dt:	04/15/2004
Title:	MULTI CHIP MODULE ASSEMBLY

Patent #:	6825556	Issue Dt:	11/30/2004	Application #:	10271003	Filing Dt:	10/15/2002
Publication #:	US20040070058	Pub Dt:	04/15/2004
Title:	INTEGRATED CIRCUIT PACKAGE DESIGN

Patent #:	6603201	Issue Dt:	08/05/2003	Application #:	10278373	Filing Dt:	10/23/2002
Title:	ELECTRONIC SUBSTRATE

Patent #:	6654248	Issue Dt:	11/25/2003	Application #:	10280566	Filing Dt:	10/25/2002
Title:	TOP GATED HEAT DISSIPATION

Patent #:	6744081	Issue Dt:	06/01/2004	Application #:	10283965	Filing Dt:	10/30/2002
Publication #:	US20040085099	Pub Dt:	05/06/2004
Title:	INTERLEAVED TERMINATION RING

Patent #:	6828643	Issue Dt:	12/07/2004	Application #:	10287668	Filing Dt:	11/04/2002
Publication #:	US20040084742	Pub Dt:	05/06/2004
Title:	BONDING PADS OVER INPUT CIRCUITS

Patent #:	6734697	Issue Dt:	05/11/2004	Application #:	10289074	Filing Dt:	11/06/2002
Publication #:	US20040085083	Pub Dt:	05/06/2004
Title:	DIE LOCATION ON UNGROUNDED WAFER FOR BACK-SIDE EMISSION MICROSCOPY

Patent #:	6943446	Issue Dt:	09/13/2005	Application #:	10290953	Filing Dt:	11/08/2002
Publication #:	US20040089953	Pub Dt:	05/13/2004
Title:	VIA CONSTRUCTION FOR STRUCTURAL SUPPORT

Patent #:	6861183	Issue Dt:	03/01/2005	Application #:	10293458	Filing Dt:	11/13/2002
Publication #:	US20040091791	Pub Dt:	05/13/2004
Title:	SCATTER DOTS

Patent #:	6648064	Issue Dt:	11/18/2003	Application #:	10298338	Filing Dt:	11/14/2002
Title:	ACTIVE HEAT SINK

Patent #:	6861748	Issue Dt:	03/01/2005	Application #:	10298971	Filing Dt:	11/18/2002
Publication #:	US20040096995	Pub Dt:	05/20/2004
Title:	TEST STRUCTURE

Patent #:	6597189	Issue Dt:	07/22/2003	Application #:	10306064	Filing Dt:	11/27/2002
Title:	SOCKETLESS/BOARDLESS TEST INTERPOSER CARD

Patent #:	NONE	Issue Dt:		Application #:	10322974	Filing Dt:	12/18/2002
Publication #:	US20030084587	Pub Dt:	05/08/2003
Title:	Substrate processing system

Patent #:	6818996	Issue Dt:	11/16/2004	Application #:	10327333	Filing Dt:	12/20/2002
Publication #:	US20040121522	Pub Dt:	06/24/2004
Title:	MULTI-LEVEL REDISTRIBUTION LAYER TRACES FOR REDUCING CURRENT CROWDING IN FLIPCHIP SOLDER BUMPS

Patent #:	6781228	Issue Dt:	08/24/2004	Application #:	10339844	Filing Dt:	01/10/2003
Publication #:	US20040135263	Pub Dt:	07/15/2004
Title:	DONUT POWER MESH SCHEME FOR FLIP CHIP PACKAGE

Patent #:	6801437	Issue Dt:	10/05/2004	Application #:	10347759	Filing Dt:	01/21/2003
Publication #:	US20040142556	Pub Dt:	07/22/2004
Title:	ELECTRONIC ORGANIC SUBSTRATE

Patent #:	6951000	Issue Dt:	09/27/2005	Application #:	10349770	Filing Dt:	01/22/2003
Publication #:	US20040143803	Pub Dt:	07/22/2004
Title:	SIMULATED VOLTAGE CONTRAST IMAGE GENERATOR AND COMPARATOR

Patent #:	6963138	Issue Dt:	11/08/2005	Application #:	10357142	Filing Dt:	02/03/2003
Publication #:	US20040150069	Pub Dt:	08/05/2004
Title:	DIELECTRIC STACK

Patent #:	6891392	Issue Dt:	05/10/2005	Application #:	10371386	Filing Dt:	02/21/2003
Publication #:	US20040164758	Pub Dt:	08/26/2004
Title:	SUBSTRATE IMPEDANCE MEASUREMENT

Patent #:	6777971	Issue Dt:	08/17/2004	Application #:	10394445	Filing Dt:	03/20/2003
Publication #:	US20030214317	Pub Dt:	11/20/2003
Title:	HIGH SPEED WAFER SORT AND FINAL TEST

Patent #:	7190082	Issue Dt:	03/13/2007	Application #:	10396955	Filing Dt:	03/24/2003
Publication #:	US20040188862	Pub Dt:	09/30/2004
Title:	LOW STRESS FLIP-CHIP PACKAGE FOR LOW-K SILICON TECHNOLOGY

Patent #:	6798069	Issue Dt:	09/28/2004	Application #:	10402054	Filing Dt:	03/28/2003
Title:	INTEGRATED CIRCUIT HAVING ADAPTABLE CORE AND INPUT/OUTPUT REGIONS WITH MULTI-LAYER PAD TRACE CONDUCTORS

Patent #:	7023225	Issue Dt:	04/04/2006	Application #:	10417049	Filing Dt:	04/16/2003
Publication #:	US20040207416	Pub Dt:	10/21/2004
Title:	WAFER-MOUNTED MICRO-PROBING PLATFORM

Patent #:	6768386	Issue Dt:	07/27/2004	Application #:	10420219	Filing Dt:	04/22/2003
Title:	DUAL CLOCK PACKAGE OPTION

Patent #:	6771085	Issue Dt:	08/03/2004	Application #:	10428200	Filing Dt:	04/30/2003
Publication #:	US20040100292	Pub Dt:	05/27/2004
Title:	SOCKETLESS/BOARDLESS TEST INTERPOSER CARD

Patent #:	6911736	Issue Dt:	06/28/2005	Application #:	10456281	Filing Dt:	06/06/2003
Publication #:	US20040245632	Pub Dt:	12/09/2004
Title:	ELECTROSTATIC DISCHARGE PROTECTION

Patent #:	6867480	Issue Dt:	03/15/2005	Application #:	10458130	Filing Dt:	06/10/2003
Publication #:	US20040251522	Pub Dt:	12/16/2004
Title:	ELECTROMAGNETIC INTERFERENCE PACKAGE PROTECTION

Patent #:	6710453	Issue Dt:	03/23/2004	Application #:	10462524	Filing Dt:	06/16/2003
Publication #:	US20030211641	Pub Dt:	11/13/2003
Title:	INTEGRATED CIRCUIT CONTAINING REDUNDANT CORE AND PERIPHERAL CONTACTS

Patent #:	6963129	Issue Dt:	11/08/2005	Application #:	10464178	Filing Dt:	06/18/2003
Title:	MULTI-CHIP PACKAGE HAVING A CONTIGUOUS HEAT SPREADER ASSEMBLY

Patent #:	6798035	Issue Dt:	09/28/2004	Application #:	10600255	Filing Dt:	06/20/2003
Title:	BONDING PAD FOR LOW K DIELECTRIC

Patent #:	6836026	Issue Dt:	12/28/2004	Application #:	10614402	Filing Dt:	07/03/2003
Title:	INTEGRATD CIRCUIT DESIGN FOR BOTH INPUT OUTPUT LIMITED AND CORE LIMITED INTEGRATED CIRCUITS

Patent #:	6744130	Issue Dt:	06/01/2004	Application #:	10615063	Filing Dt:	07/08/2003
Title:	ISOLATED STRIPLINE STRUCTURE

Patent #:	6933602	Issue Dt:	08/23/2005	Application #:	10620074	Filing Dt:	07/14/2003
Title:	SEMICONDUCTOR PACKAGE HAVING A THERMALLY AND ELECTRICALLY CONNECTED HEATSPREADER

Patent #:	6806119	Issue Dt:	10/19/2004	Application #:	10631328	Filing Dt:	07/30/2003
Publication #:	US20040121519	Pub Dt:	06/24/2004
Title:	METHOD OF BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY

Patent #:	6828682	Issue Dt:	12/07/2004	Application #:	10635276	Filing Dt:	08/06/2003
Title:	SUBSTRATE VOLTAGE CONNECTION

Patent #:	6858930	Issue Dt:	02/22/2005	Application #:	10638772	Filing Dt:	08/11/2003
Publication #:	US20040065951	Pub Dt:	04/08/2004
Title:	MULTI CHIP MODULE

Patent #:	6991147	Issue Dt:	01/31/2006	Application #:	10642706	Filing Dt:	08/18/2003
Publication #:	US20040182911	Pub Dt:	09/23/2004
Title:	INSULATED BONDING WIRE TOOL FOR MICROELECTRONIC PACKAGING

Patent #:	7148535	Issue Dt:	12/12/2006	Application #:	10647863	Filing Dt:	08/25/2003
Publication #:	US20050046029	Pub Dt:	03/03/2005
Title:	ZERO CAPACITANCE BONDPAD UTILIZING ACTIVE NEGATIVE CAPACITANCE

Patent #:	6743979	Issue Dt:	06/01/2004	Application #:	10652453	Filing Dt:	08/29/2003
Title:	BONDING PAD ISOLATION

Patent #:	7009282	Issue Dt:	03/07/2006	Application #:	10672495	Filing Dt:	09/26/2003
Publication #:	US20050067677	Pub Dt:	03/31/2005
Title:	PACKAGED INTEGRATED CIRCUIT PROVIDING TRACE ACCESS TO HIGH-SPEED LEADS

Patent #:	7056819	Issue Dt:	06/06/2006	Application #:	10673703	Filing Dt:	09/29/2003
Publication #:	US20050067678	Pub Dt:	03/31/2005
Title:	METHODS AND APPARATUS FOR DETERMINING PAD HEIGHT FOR A WIRE-BONDING OPERATION IN AN INTEGRATED CIRCUIT

Patent #:	6960836	Issue Dt:	11/01/2005	Application #:	10675260	Filing Dt:	09/30/2003
Publication #:	US20050067709	Pub Dt:	03/31/2005
Title:	REINFORCED BOND PAD

Patent #:	6979869	Issue Dt:	12/27/2005	Application #:	10676602	Filing Dt:	10/01/2003
Publication #:	US20050082621	Pub Dt:	04/21/2005
Title:	SUBSTRATE-BIASED I/O AND POWER ESD PROTECTION CIRCUITS IN DEEP-SUBMICRON TWIN-WELL PROCESS

Patent #:	7345245	Issue Dt:	03/18/2008	Application #:	10681554	Filing Dt:	10/08/2003
Publication #:	US20050077081	Pub Dt:	04/14/2005
Title:	ROBUST HIGH DENSITY SUBSTRATE DESIGN FOR THERMAL CYCLING RELIABILITY

Patent #:	6825563	Issue Dt:	11/30/2004	Application #:	10683101	Filing Dt:	10/09/2003
Title:	SLOTTED BONDING PAD

Patent #:	NONE	Issue Dt:		Application #:	10694486	Filing Dt:	10/27/2003
Publication #:	US20040089938	Pub Dt:	05/13/2004
Title:	Bonding pad design

Patent #:	6987052	Issue Dt:	01/17/2006	Application #:	10697757	Filing Dt:	10/30/2003
Publication #:	US20050093097	Pub Dt:	05/05/2005
Title:	METHOD FOR MAKING ENHANCED SUBSTRATE CONTACT FOR A SEMICONDUCTOR DEVICE

Patent #:	7314781	Issue Dt:	01/01/2008	Application #:	10702875	Filing Dt:	11/05/2003
Publication #:	US20060172456	Pub Dt:	08/03/2006
Title:	DEVICE PACKAGES HAVING STABLE WIREBONDS

Patent #:	7791210	Issue Dt:	09/07/2010	Application #:	10702996	Filing Dt:	11/05/2003
Publication #:	US20050093173	Pub Dt:	05/05/2005
Title:	SEMICONDUCTOR PACKAGE HAVING DISCRETE NON-ACTIVE ELECTRICAL COMPONENTS INCORPORATED INTO THE PACKAGE

Patent #:	7082585	Issue Dt:	07/25/2006	Application #:	10718829	Filing Dt:	11/21/2003
Publication #:	US20050114806	Pub Dt:	05/26/2005
Title:	ANALYSIS OF INTEGRATED CIRCUITS FOR HIGH FREQUENCY PERFORMANCE

Patent #:	7429703	Issue Dt:	09/30/2008	Application #:	10722652	Filing Dt:	11/26/2003
Publication #:	US20050109525	Pub Dt:	05/26/2005
Title:	METHODS AND APPARATUS FOR INTEGRATED CIRCUIT DEVICE POWER DISTRIBUTION VIA INTERNAL WIRE BONDS

Patent #:	6954082	Issue Dt:	10/11/2005	Application #:	10727474	Filing Dt:	12/04/2003
Publication #:	US20050122127	Pub Dt:	06/09/2005
Title:	METHOD AND APPARATUS FOR TESTING OF INTEGRATED CIRCUIT PACKAGE

Patent #:	7328830	Issue Dt:	02/12/2008	Application #:	10741155	Filing Dt:	12/19/2003
Publication #:	US20040182915	Pub Dt:	09/23/2004
Title:	STRUCTURE AND METHOD FOR BONDING TO COPPER INTERCONNECT STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	10742916	Filing Dt:	12/23/2003
Publication #:	US20040163244	Pub Dt:	08/26/2004
Title:	Method of manufacturing and mounting electronic devices to limit the effects of parasitics

Patent #:	7098528	Issue Dt:	08/29/2006	Application #:	10744363	Filing Dt:	12/22/2003
Publication #:	US20050133935	Pub Dt:	06/23/2005
Title:	EMBEDDED REDISTRIBUTION INTERPOSER FOR FOOTPRINT COMPATIBLE CHIP PACKAGE CONVERSION

Patent #:	7456716	Issue Dt:	11/25/2008	Application #:	10746824	Filing Dt:	12/24/2003
Publication #:	US20050146413	Pub Dt:	07/07/2005
Title:	ELECTRICAL DEVICES HAVING ADJUSTABLE ELECTRICAL CHARACTERISTICS

Patent #:	NONE	Issue Dt:		Application #:	10755616	Filing Dt:	01/12/2004
Publication #:	US20050150682	Pub Dt:	07/14/2005
Title:	Method for electrical interconnection between printed wiring board layers using through holes with solid core conductive material

Patent #:	7074705	Issue Dt:	07/11/2006	Application #:	10786182	Filing Dt:	02/25/2004
Publication #:	US20050176232	Pub Dt:	08/11/2005
Title:	METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING WITH SUBSTANTIALLY PERPENDICULAR WIRE BOND PROFILES

Patent #:	7086148	Issue Dt:	08/08/2006	Application #:	10787010	Filing Dt:	02/25/2004
Publication #:	US20050183265	Pub Dt:	08/25/2005
Title:	METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT

Patent #:	7075174	Issue Dt:	07/11/2006	Application #:	10788162	Filing Dt:	02/26/2004
Publication #:	US20050191793	Pub Dt:	09/01/2005
Title:	SEMICONDUCTOR PACKAGING TECHNIQUES FOR USE WITH NON-CERAMIC PACKAGES

Patent #:	7164200	Issue Dt:	01/16/2007	Application #:	10788678	Filing Dt:	02/27/2004
Publication #:	US20050189616	Pub Dt:	09/01/2005
Title:	TECHNIQUES FOR REDUCING BOWING IN POWER TRANSISTOR DEVICES

Patent #:	7041561	Issue Dt:	05/09/2006	Application #:	10814062	Filing Dt:	03/31/2004
Publication #:	US20050221563	Pub Dt:	10/06/2005
Title:	ENHANCED SUBSTRATE CONTACT FOR A SEMICONDUCTOR DEVICE

Patent #:	7030472	Issue Dt:	04/18/2006	Application #:	10816060	Filing Dt:	04/01/2004
Publication #:	US20050224926	Pub Dt:	10/13/2005
Title:	INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME

Patent #:	7173328	Issue Dt:	02/06/2007	Application #:	10819684	Filing Dt:	04/06/2004
Publication #:	US20050224964	Pub Dt:	10/13/2005
Title:	INTEGRATED CIRCUIT PACKAGE AND METHOD HAVING WIRE-BONDED INTRA-DIE ELECTRICAL CONNECTIONS

Patent #:	6894400	Issue Dt:	05/17/2005	Application #:	10853395	Filing Dt:	05/25/2004
Title:	ROBUST ELECTRONIC DEVICE PACKAGES

Patent #:	7368326	Issue Dt:	05/06/2008	Application #:	10855148	Filing Dt:	05/27/2004
Publication #:	US20050153532	Pub Dt:	07/14/2005
Title:	METHODS AND APPARATUS TO REDUCE GROWTH FORMATIONS ON PLATED CONDUCTIVE LEADS

Patent #:	6998638	Issue Dt:	02/14/2006	Application #:	10856213	Filing Dt:	05/28/2004
Publication #:	US20040217487	Pub Dt:	11/04/2004
Title:	TEST STRUCTURE FOR DETECTING BONDING-INDUCED CRACKS

Patent #:	7436060	Issue Dt:	10/14/2008	Application #:	10865179	Filing Dt:	06/09/2004
Publication #:	US20050275086	Pub Dt:	12/15/2005
Title:	SEMICONDUCTOR PACKAGE AND PROCESS UTILIZING PRE-FORMED MOLD CAP AND HEATSPREADER ASSEMBLY

Patent #:	7157361	Issue Dt:	01/02/2007	Application #:	10878157	Filing Dt:	06/28/2004
Publication #:	US20060014370	Pub Dt:	01/19/2006
Title:	METHODS FOR PROCESSING INTEGRATED CIRCUIT PACKAGES FORMED USING ELECTROPLATING AND APPARATUS MADE THEREFROM

Patent #:	7745927	Issue Dt:	06/29/2010	Application #:	10879909	Filing Dt:	06/29/2004
Publication #:	US20050287952	Pub Dt:	12/29/2005
Title:	HEAT SINK FORMED OF MULTIPLE METAL LAYERS ON BACKSIDE OF INTEGRATED CIRCUIT DIE

Patent #:	7009305	Issue Dt:	03/07/2006	Application #:	10881191	Filing Dt:	06/30/2004
Publication #:	US20060001157	Pub Dt:	01/05/2006
Title:	METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING USING STACKED BALL BUMPS

Patent #:	7096748	Issue Dt:	08/29/2006	Application #:	10900869	Filing Dt:	07/28/2004
Publication #:	US20060021453	Pub Dt:	02/02/2006
Title:	EMBEDDED STRAIN GAUGE IN PRINTED CIRCUIT BOARDS

Patent #:	7117467	Issue Dt:	10/03/2006	Application #:	10918933	Filing Dt:	08/16/2004
Publication #:	US20060036987	Pub Dt:	02/16/2006
Title:	METHODS FOR OPTIMIZING PACKAGE AND SILICON CO-DESIGN OF INTEGRATED CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	10921497	Filing Dt:	08/18/2004
Publication #:	US20050017368	Pub Dt:	01/27/2005
Title:	Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps

Patent #:	7109589	Issue Dt:	09/19/2006	Application #:	10926631	Filing Dt:	08/26/2004
Publication #:	US20060043609	Pub Dt:	03/02/2006
Title:	INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS

Patent #:	8404960	Issue Dt:	03/26/2013	Application #:	10930590	Filing Dt:	08/31/2004
Publication #:	US20060043582	Pub Dt:	03/02/2006
Title:	METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE

100

Patent #:	7235889	Issue Dt:	06/26/2007	Application #:	10939082	Filing Dt:	09/10/2004
Publication #:	US20060055029	Pub Dt:	03/16/2006
Title:	INTEGRATED HEATSPREADER FOR USE IN WIRE BONDED BALL GRID ARRAY SEMICONDUCTOR PACKAGES

Assignors

AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Exec Dt:

12/08/2017

BROADCOM CORPORATION

Exec Dt:

12/08/2017

Assignee

BELL SEMICONDUCTOR, LLC

401 N. MICHIGAN AVE.

SUITE 1600

CHICAGO, ILLINOIS 60611

Correspondence name and address
	CHAD S. HILYARD
	401 N. MICHIGAN AVE.
	SUITE 1600
	CHICAGO, IL 60611

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