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Total properties:
15
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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09699138
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Filing Dt:
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10/27/2000
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Title:
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METHOD AND APPARATUS FOR PARALLEL CARRY CHAINS
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09724839
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Filing Dt:
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11/28/2000
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Title:
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DESIGN INSTRUMENTATION CIRCUITRY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09724840
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Filing Dt:
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11/28/2000
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Title:
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METHOD AND SYSTEM FOR PROVIDING AN ELECTRONIC SYSTEM DESIGN WITH ENHANCED DEBUGGING CAPABILITIES
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09730990
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Filing Dt:
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12/05/2000
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Title:
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METHODS AND APPAATUSES FOR DESIGNING INTEGRATED CIRCUITS USING AUTOMATIC REALLOCATION TECHNIQUES
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09828394
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Filing Dt:
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04/05/2001
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Title:
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METHOD AND APPARATUS FOR INVALID STATE DETECTION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10016214
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Filing Dt:
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12/06/2001
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Title:
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REDUCING CLOCK SKEW IN CLOCK GATING CIRCUITS
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10020546
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Filing Dt:
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10/29/2001
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Title:
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METHODS AND APPARATUSES FOR CHECKING EQUIVALENCE OF CIRCUITS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10066093
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Filing Dt:
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01/31/2002
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Title:
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METHODS AND APPARATUSES FOR NON-EQUIVALENCE CHECKING OF CIRCUITS WITH SUBSPACE
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10091787
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Filing Dt:
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03/04/2002
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Title:
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METHOD AND APPARATUS FOR RESETABLE MEMORY AND DESIGN APPROACH FOR SAME
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Patent #:
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Issue Dt:
|
05/11/2004
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Application #:
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10132996
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Filing Dt:
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04/25/2002
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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POWER AND GROUND SHIELD MESH TO REMOVE BOTH CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS OF ROUTING IN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10162270
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUITS
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|
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10210509
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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07/10/2003
| | | | |
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Title:
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METHOD AND USER INTERFACE FOR DEBUGGING AN ELECTRONIC SYSTEM
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10215869
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Filing Dt:
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08/09/2002
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
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Title:
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METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC
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|
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Patent #:
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Issue Dt:
|
05/04/2004
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Application #:
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10318589
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Filing Dt:
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12/13/2002
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Title:
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LOCAL NAMING FOR HDL COMPILATION
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Patent #:
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Issue Dt:
|
06/07/2005
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Application #:
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10406732
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Filing Dt:
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04/02/2003
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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HARDWARE DEBUGGING IN A HARDWARE DESCRIPTION LANGUAGE
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