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Patent Assignment Details
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Reel/Frame:013735/0791   Pages: 7
Recorded: 02/06/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 23
1
Patent #:
Issue Dt:
09/03/1991
Application #:
07019418
Filing Dt:
02/26/1987
Title:
VECTOR CALCULATOR APPARATUS FOR GRAPHIC WAVEFORM MANIPULATION
2
Patent #:
Issue Dt:
09/19/1989
Application #:
07127775
Filing Dt:
12/02/1987
Title:
SIMULATION RESULTS ENHANCEMENT METHOD AND SYSTEM
3
Patent #:
Issue Dt:
01/15/1991
Application #:
07369358
Filing Dt:
06/21/1989
Title:
MIXED-MODE-SIMULATOR INTERFACE
4
Patent #:
Issue Dt:
03/30/1993
Application #:
07689953
Filing Dt:
04/23/1991
Title:
VECTOR CALCULATOR APPARATUS FOR GRAPHIC WAVEFORM MANIPULATION
5
Patent #:
Issue Dt:
08/08/1995
Application #:
07859578
Filing Dt:
03/27/1992
Title:
SYSTEM FOR DETERMINING THE OPERATIONS OF AN INTEGRATED CIRCUIT AND PROCESSOR FOR USE THEREIN
6
Patent #:
Issue Dt:
04/04/1995
Application #:
07991646
Filing Dt:
02/11/1993
Title:
TRANSLATION OF BEHAVIORAL MODELING PROPERTIES INTO AN ANALOG HARDWARE DESCRIPTION LANGUAGE
7
Patent #:
Issue Dt:
01/09/1996
Application #:
08074961
Filing Dt:
06/10/1993
Title:
ROUTING ALGORITHM METHOD FOR STANDARD-CELL AND GATE-ARRAY INTEGRATED CIRCUIT DESIGN
8
Patent #:
Issue Dt:
10/24/1995
Application #:
08115995
Filing Dt:
09/01/1993
Title:
ELECTRONIC DESIGN AUTOMATION TOOL FOR THE DESIGN OF A SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
9
Patent #:
Issue Dt:
08/20/1996
Application #:
08148697
Filing Dt:
11/05/1993
Title:
ANALYSIS MECHANISM FOR SYSTEM PERFORMANCE SIMULATOR
10
Patent #:
Issue Dt:
03/09/1999
Application #:
08572041
Filing Dt:
12/14/1995
Title:
APPARATUS USING SCORING ADVISORS HAVING OUTPUTS COMBINED ON A BACK PLANE FOR EVALUATING DESIGNS
11
Patent #:
Issue Dt:
10/05/1999
Application #:
08602223
Filing Dt:
02/16/1996
Title:
COMPONENT-BASED ANALOG AND MIXED-SIGNAL SIMULATION MODEL DEVELOPMENT
12
Patent #:
Issue Dt:
11/24/1998
Application #:
08614129
Filing Dt:
03/12/1996
Title:
METHOD FOR OPTIMIZING TRACK ASSIGNMENT IN A GRID-BASED CHANNEL ROUTER
13
Patent #:
Issue Dt:
08/11/1998
Application #:
08643061
Filing Dt:
04/30/1996
Title:
METHOD FOR HANDLING VARIABLE WIDTH WIRES IN A GRID-BASED CHANNEL ROUTER
14
Patent #:
Issue Dt:
08/25/1998
Application #:
08666119
Filing Dt:
06/21/1996
Title:
CONGESTION-DRIVEN PLACEMENT METHOD AND COMPUTER-IMPLEMENTED INTEGRATED-CIRCUIT DESIGN TOOL
15
Patent #:
Issue Dt:
12/08/1998
Application #:
08691607
Filing Dt:
08/02/1996
Title:
METHOD FOR AUTOMATIC ITERACTIVE AREA PLACEMENT OF MODULE CELLS IN AN INTEGRATED CIRCUIT LAYOUT
16
Patent #:
Issue Dt:
04/20/1999
Application #:
08706182
Filing Dt:
08/30/1996
Title:
METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING POST-LAYOUT VERIFICATION OF MICROELECTRONIC CIRCUITS BY FILTERING TIMING ERROR BOUNDS FOR LAYOUT CRITICAL NETS.
17
Patent #:
Issue Dt:
12/14/1999
Application #:
08748764
Filing Dt:
11/14/1996
Title:
SYMBOLIC CONSTRAINT-BASED SYSTEM FOR PREROUTE RECONSTRUCTION FOLLOWING FLOORPLAN INCREMENTING
18
Patent #:
Issue Dt:
06/27/2000
Application #:
09001715
Filing Dt:
12/31/1997
Title:
PROXIMITY CORRECTION SYSTEM FOR WAFER LITHOGRAPHY
19
Patent #:
Issue Dt:
12/28/1999
Application #:
09035271
Filing Dt:
03/05/1998
Title:
METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING EQUIVALENCIES BETWEEN INTEGRATED CIRCUIT SCHEMATICS AND LAYOUTS USING COLOR SYMMETRIZING MATRICES
20
Patent #:
Issue Dt:
02/29/2000
Application #:
09087751
Filing Dt:
05/29/1998
Title:
PHASE LOCKED LOOP WITH DIGITAL VERNIER CONTROL
21
Patent #:
Issue Dt:
09/04/2001
Application #:
09292783
Filing Dt:
04/13/1999
Title:
METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING POST-LAYOUT VERIFICATION OF MICROELECTRONIC CIRCUITS USING BEST AND WORST CASE DELAY MODELS FOR NETS THERIN
22
Patent #:
Issue Dt:
05/22/2001
Application #:
09305238
Filing Dt:
05/04/1999
Title:
COMPONENT-BASED ANALOG AND MIXED-SIGNAL SIMULATION MODEL DEVELOPMENT INCLUDING NEWTON STEP MANAGER
23
Patent #:
Issue Dt:
09/11/2001
Application #:
09479340
Filing Dt:
01/07/2000
Title:
PROXIMITY CORRECTION SOFTWARE FOR WAFER LITHOGRAPHY
Assignor
1
Exec Dt:
06/11/2002
Assignee
1
700 EAST MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
SILICON VALLEY PATENT GROUP LLP
OMKAR K. SURYADEVARA
2350 MISSION COLLEGE BOULEVARD, STE. 360
SANTA CLARA, CA 95054

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