Total properties:
23
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Patent #:
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Issue Dt:
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09/03/1991
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Application #:
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07019418
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Filing Dt:
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02/26/1987
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Title:
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VECTOR CALCULATOR APPARATUS FOR GRAPHIC WAVEFORM MANIPULATION
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Patent #:
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Issue Dt:
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09/19/1989
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Application #:
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07127775
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Filing Dt:
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12/02/1987
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Title:
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SIMULATION RESULTS ENHANCEMENT METHOD AND SYSTEM
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Patent #:
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Issue Dt:
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01/15/1991
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Application #:
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07369358
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Filing Dt:
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06/21/1989
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Title:
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MIXED-MODE-SIMULATOR INTERFACE
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Patent #:
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Issue Dt:
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03/30/1993
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Application #:
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07689953
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Filing Dt:
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04/23/1991
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Title:
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VECTOR CALCULATOR APPARATUS FOR GRAPHIC WAVEFORM MANIPULATION
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Patent #:
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Issue Dt:
|
08/08/1995
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Application #:
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07859578
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Filing Dt:
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03/27/1992
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Title:
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SYSTEM FOR DETERMINING THE OPERATIONS OF AN INTEGRATED CIRCUIT AND PROCESSOR FOR USE THEREIN
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Patent #:
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Issue Dt:
|
04/04/1995
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Application #:
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07991646
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Filing Dt:
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02/11/1993
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Title:
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TRANSLATION OF BEHAVIORAL MODELING PROPERTIES INTO AN ANALOG HARDWARE DESCRIPTION LANGUAGE
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Patent #:
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Issue Dt:
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01/09/1996
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Application #:
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08074961
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Filing Dt:
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06/10/1993
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Title:
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ROUTING ALGORITHM METHOD FOR STANDARD-CELL AND GATE-ARRAY INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
10/24/1995
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Application #:
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08115995
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Filing Dt:
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09/01/1993
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Title:
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ELECTRONIC DESIGN AUTOMATION TOOL FOR THE DESIGN OF A SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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08/20/1996
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Application #:
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08148697
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Filing Dt:
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11/05/1993
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Title:
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ANALYSIS MECHANISM FOR SYSTEM PERFORMANCE SIMULATOR
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Patent #:
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|
Issue Dt:
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03/09/1999
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Application #:
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08572041
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Filing Dt:
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12/14/1995
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Title:
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APPARATUS USING SCORING ADVISORS HAVING OUTPUTS COMBINED ON A BACK PLANE FOR EVALUATING DESIGNS
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Patent #:
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|
Issue Dt:
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10/05/1999
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Application #:
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08602223
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Filing Dt:
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02/16/1996
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Title:
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COMPONENT-BASED ANALOG AND MIXED-SIGNAL SIMULATION MODEL DEVELOPMENT
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Patent #:
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Issue Dt:
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11/24/1998
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Application #:
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08614129
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Filing Dt:
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03/12/1996
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Title:
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METHOD FOR OPTIMIZING TRACK ASSIGNMENT IN A GRID-BASED CHANNEL ROUTER
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08643061
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Filing Dt:
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04/30/1996
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Title:
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METHOD FOR HANDLING VARIABLE WIDTH WIRES IN A GRID-BASED CHANNEL ROUTER
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Patent #:
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Issue Dt:
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08/25/1998
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Application #:
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08666119
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Filing Dt:
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06/21/1996
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Title:
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CONGESTION-DRIVEN PLACEMENT METHOD AND COMPUTER-IMPLEMENTED INTEGRATED-CIRCUIT DESIGN TOOL
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|
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Patent #:
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Issue Dt:
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12/08/1998
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Application #:
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08691607
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Filing Dt:
|
08/02/1996
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Title:
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METHOD FOR AUTOMATIC ITERACTIVE AREA PLACEMENT OF MODULE CELLS IN AN INTEGRATED CIRCUIT LAYOUT
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|
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Patent #:
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|
Issue Dt:
|
04/20/1999
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Application #:
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08706182
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Filing Dt:
|
08/30/1996
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Title:
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METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING POST-LAYOUT VERIFICATION OF MICROELECTRONIC CIRCUITS BY FILTERING TIMING ERROR BOUNDS FOR LAYOUT CRITICAL NETS.
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Patent #:
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|
Issue Dt:
|
12/14/1999
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Application #:
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08748764
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Filing Dt:
|
11/14/1996
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Title:
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SYMBOLIC CONSTRAINT-BASED SYSTEM FOR PREROUTE RECONSTRUCTION FOLLOWING FLOORPLAN INCREMENTING
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|
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Patent #:
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|
Issue Dt:
|
06/27/2000
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Application #:
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09001715
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Filing Dt:
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12/31/1997
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Title:
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PROXIMITY CORRECTION SYSTEM FOR WAFER LITHOGRAPHY
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Patent #:
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|
Issue Dt:
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12/28/1999
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Application #:
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09035271
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Filing Dt:
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03/05/1998
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Title:
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METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING EQUIVALENCIES BETWEEN INTEGRATED CIRCUIT SCHEMATICS AND LAYOUTS USING COLOR SYMMETRIZING MATRICES
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Patent #:
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|
Issue Dt:
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02/29/2000
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Application #:
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09087751
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Filing Dt:
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05/29/1998
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Title:
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PHASE LOCKED LOOP WITH DIGITAL VERNIER CONTROL
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Patent #:
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Issue Dt:
|
09/04/2001
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Application #:
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09292783
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Filing Dt:
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04/13/1999
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Title:
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METHODS, APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING POST-LAYOUT VERIFICATION OF MICROELECTRONIC CIRCUITS USING BEST AND WORST CASE DELAY MODELS FOR NETS THERIN
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|
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Patent #:
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|
Issue Dt:
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05/22/2001
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Application #:
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09305238
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Filing Dt:
|
05/04/1999
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Title:
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COMPONENT-BASED ANALOG AND MIXED-SIGNAL SIMULATION MODEL DEVELOPMENT INCLUDING NEWTON STEP MANAGER
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|
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Patent #:
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|
Issue Dt:
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09/11/2001
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Application #:
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09479340
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Filing Dt:
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01/07/2000
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Title:
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PROXIMITY CORRECTION SOFTWARE FOR WAFER LITHOGRAPHY
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