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Total properties:
15
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Patent #:
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|
Issue Dt:
|
02/27/2001
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Application #:
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09213674
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Filing Dt:
|
12/17/1998
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Title:
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QUANTUM CONDUCTIVE RECRYSTALLIZATION BARRIER LAYERS
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Patent #:
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|
Issue Dt:
|
10/19/2004
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Application #:
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10137274
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Filing Dt:
|
05/01/2002
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Publication #:
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Pub Dt:
|
11/06/2003
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Title:
|
METHOD FOR ELIMINATING VIA RESISTANCE SHIFT IN ORGANIC ILD
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|
|
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Patent #:
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|
Issue Dt:
|
05/10/2005
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Application #:
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10397761
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Filing Dt:
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03/26/2003
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Publication #:
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Pub Dt:
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09/30/2004
| | | | |
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Title:
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TRENCH ISOLATION EMPLOYING A DOPED OXIDE TRENCH FILL
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Patent #:
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Issue Dt:
|
11/30/2004
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Application #:
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10411728
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Filing Dt:
|
04/11/2003
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
|
SCANNING TIP ORIENTATION ADJUSTMENT METHOD FOR ATOMIC FORCE MICROSCOPY
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10438352
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Filing Dt:
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05/14/2003
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Publication #:
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Pub Dt:
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01/01/2004
| | | | |
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Title:
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CIRCUIT WITH BURIED STRAP INCLUDING LINER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10457217
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Filing Dt:
|
06/09/2003
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
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Title:
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Composite low-k dielectric structure
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Patent #:
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Issue Dt:
|
08/16/2005
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Application #:
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10463023
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Filing Dt:
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06/16/2003
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Publication #:
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Pub Dt:
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12/16/2004
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Title:
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AN ACTIVE SOI STRUCTURE WITH A BODY CONTACT THROUGH AN INSULATOR
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Patent #:
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Issue Dt:
|
07/10/2007
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Application #:
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10605927
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Filing Dt:
|
11/06/2003
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Publication #:
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Pub Dt:
|
05/12/2005
| | | | |
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Title:
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METHOD FOR PERFORMING A BURN-IN TEST
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|
|
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Patent #:
|
|
Issue Dt:
|
11/02/2004
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Application #:
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10610609
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Filing Dt:
|
07/01/2003
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Title:
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RECESSED METAL LINES FOR PROTECTIVE ENCLOSURE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
01/04/2005
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Application #:
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10618333
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Filing Dt:
|
07/11/2003
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|
Publication #:
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Pub Dt:
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01/13/2005
| | | | |
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Title:
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STRUCTURE AND METHOD OF MULTIPLEXING BITLINE SIGNALS WITHIN A MEMORY ARRAY
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
10619884
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Filing Dt:
|
07/15/2003
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Publication #:
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Pub Dt:
|
01/20/2005
| | | | |
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Title:
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Method to improve bitline contact formation using a line mask
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/25/2005
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Application #:
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10631394
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Filing Dt:
|
07/31/2003
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|
Publication #:
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Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
OFF CHIP DRIVER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
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Application #:
|
10654143
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Filing Dt:
|
09/03/2003
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|
Publication #:
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|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
SEALED PORES IN LOW-K MATERIAL DAMASCENE CONDUCTIVE STRUCTURES
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10661248
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Filing Dt:
|
09/12/2003
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|
Publication #:
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|
Pub Dt:
|
03/17/2005
| | | | |
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Title:
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Wafer processing techniques with enhanced alignment
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/17/2006
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Application #:
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10741203
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Filing Dt:
|
12/19/2003
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|
Publication #:
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|
Pub Dt:
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06/23/2005
| | | | |
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Title:
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DEEP TRENCH CAPACITOR WITH BURIED PLATE ELECTRODE AND ISOLATION COLLAR
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|
