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Patent Assignment Details
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Reel/Frame:021138/0799   Pages: 18
Recorded: 06/20/2008
Attorney Dkt #:02986.G056
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 15
1
Patent #:
Issue Dt:
03/25/2008
Application #:
10351094
Filing Dt:
01/23/2003
Title:
METHOD AND APPARATUS FOR PLACEMENT AND ROUTING CELLS ON INTEGRATED CIRCUIT CHIPS
2
Patent #:
Issue Dt:
05/22/2007
Application #:
10377907
Filing Dt:
02/28/2003
Publication #:
Pub Dt:
02/05/2004
Title:
HARDWARE-BASED HDL CODE COVERAGE AND DESIGN ANALYSIS
3
Patent #:
Issue Dt:
09/25/2007
Application #:
10382342
Filing Dt:
03/04/2003
Publication #:
Pub Dt:
08/07/2003
Title:
METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUITS
4
Patent #:
Issue Dt:
01/09/2007
Application #:
10435061
Filing Dt:
05/09/2003
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD AND APPARATUS FOR CIRCUIT DESIGN AND RETIMING
5
Patent #:
Issue Dt:
07/03/2007
Application #:
10456768
Filing Dt:
06/06/2003
Title:
HARDWARE/SOFTWARE CO-DEBUGGING IN A HARDWARE DESCRIPTION LANGUAGE
6
Patent #:
Issue Dt:
04/03/2007
Application #:
10758977
Filing Dt:
01/14/2004
Title:
CIRCUITS WITH MODULAR REDUNDANCY AND METHODS AND APPARATUSES FOR THEIR AUTOMATED SYNTHESIS
7
Patent #:
Issue Dt:
06/26/2007
Application #:
10792933
Filing Dt:
03/03/2004
Title:
METHOD AND APPARATUS FOR CIRCUIT PARTITIONING AND TRACE ASSIGNMENT IN CIRCUIT DESIGN
8
Patent #:
Issue Dt:
05/15/2007
Application #:
10810748
Filing Dt:
03/26/2004
Publication #:
Pub Dt:
09/16/2004
Title:
POWER AND GROUND SHIELD MESH TO REMOVE BOTH CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS OF ROUTING IN INTEGRATED CIRCUIT DEVICE
9
Patent #:
Issue Dt:
02/13/2007
Application #:
10850808
Filing Dt:
05/21/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND APPARATUS FOR AUTOMATED CIRCUIT DESIGN
10
Patent #:
Issue Dt:
07/31/2007
Application #:
10856280
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD AND APPARATUS FOR AUTOMATED CIRCUIT DESIGN
11
Patent #:
Issue Dt:
10/02/2007
Application #:
10897459
Filing Dt:
07/23/2004
Publication #:
Pub Dt:
02/09/2006
Title:
METHODS AND APPARATUSES FOR TRANSIENT ANALYSES OF CIRCUITS
12
Patent #:
Issue Dt:
08/28/2007
Application #:
10911317
Filing Dt:
08/03/2004
Title:
METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS AND OPTIMIZATION OF DATAPATHS
13
Patent #:
Issue Dt:
04/08/2008
Application #:
10915516
Filing Dt:
08/09/2004
Publication #:
Pub Dt:
01/13/2005
Title:
METHOD AND USER INTERFACE FOR DEBUGGING AN ELECTRONIC SYSTEM
14
Patent #:
Issue Dt:
04/29/2008
Application #:
11034391
Filing Dt:
01/11/2005
Title:
METHODS AND APPARATUSES FOR THERMAL ANALYSIS BASED CIRCUIT DESIGN
15
Patent #:
Issue Dt:
05/01/2007
Application #:
11112092
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
08/24/2006
Title:
METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC
Assignor
1
Exec Dt:
05/15/2008
Assignee
1
700 E. MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
JAMES C. SCHELLER, JR.
BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP
1279 OAKMEAD PARKWAY
SUNNYVALE, CA 94085

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