|
Total properties:
87
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/1990
|
Application #:
|
07259830
|
Filing Dt:
|
10/19/1988
|
|
Title:
|
GROUP III - V SEMICONDUCTOR DEVICES WITH IMPROVED SWITCHING SPEEDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/1990
|
Application #:
|
07294271
|
Filing Dt:
|
01/06/1989
|
|
Title:
|
CURRENT-STEERING FET LOGIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1992
|
Application #:
|
07618992
|
Filing Dt:
|
11/28/1990
|
|
Title:
|
GATE-TO-OHMIC METAL CONTACT SCHEME FOR III-V DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1992
|
Application #:
|
07622227
|
Filing Dt:
|
12/03/1990
|
|
Title:
|
STATIC RAM CELL WITH HIGH SPEED AND IMPROVED CELL STABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1993
|
Application #:
|
07645981
|
Filing Dt:
|
01/23/1991
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING CLOCK SKEW
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1992
|
Application #:
|
07702151
|
Filing Dt:
|
05/14/1991
|
|
Title:
|
OHMIC CONTACT FOR III-V SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1993
|
Application #:
|
07742300
|
Filing Dt:
|
08/08/1991
|
|
Title:
|
IMPROVED HIGH SPEED LOGIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
07877253
|
Filing Dt:
|
04/28/1992
|
|
Title:
|
PROCESS FOR FORMING OHMIC CONTACT FOR III-V SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/1997
|
Application #:
|
08273572
|
Filing Dt:
|
07/11/1994
|
|
Title:
|
DISTRIBUTED RAMP DELAY GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08558108
|
Filing Dt:
|
11/13/1995
|
|
Title:
|
LOGIC GATES FOR REDUCING POWER CONSUMPTION OF GALLIUM ARSENIDE INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08575115
|
Filing Dt:
|
12/19/1995
|
|
Title:
|
DIGITAL LOGIC OUTPUT BUFFER INTERFACE FOR DIFFERENT SEMICONDUCTOR TECHNOLOGIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08845272
|
Filing Dt:
|
04/24/1997
|
|
Title:
|
MEDIA ACCESS CONTROL RECEIVER AND NETWORK MANAGEMENT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08845562
|
Filing Dt:
|
04/24/1997
|
|
Title:
|
MEDIA ACCESS CONTROL ARCHITECTURES AND NETWORK MANAGEMENT SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08845563
|
Filing Dt:
|
04/24/1997
|
|
Title:
|
MEDIA ACCESS CONTROL TRANSMITTER AND PARALLEL NETWORK MANAGEMENT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08863875
|
Filing Dt:
|
05/27/1997
|
|
Title:
|
BUS ARRANGEMENTS FOR INTERCONNECTION OF DISCRETE AND/OR INTEGRATED MODULES IN A DIGITAL SYSTEM AND ASSOCIATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
08942011
|
Filing Dt:
|
10/01/1997
|
|
Title:
|
SYNCHRONOUS LATCHING BUS ARRANGEMENT FOR INTERFACING DISCRETE AND/OR INTEGRATED MODULES IN A DIGITAL SYSTEM AND ASSOCIATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
08968551
|
Filing Dt:
|
11/12/1997
|
|
Title:
|
MEDIA ACCESS CONTROL MICRO-RISC STREAM PROCESSOR AND METHOD FOR IMPLEMENTING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09047888
|
Filing Dt:
|
03/25/1998
|
|
Title:
|
CIRCUIT AND TECHNIQUE FOR DIGITAL REDUCTION OF JITTER TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09067584
|
Filing Dt:
|
04/27/1998
|
|
Title:
|
PRIORITY ALLOCATION IN A BUS INTERCONNECTED DISCRETE AND/OR INTERGRATED DIGITAL MULTI-MODULE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09129662
|
Filing Dt:
|
08/05/1998
|
|
Title:
|
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09139252
|
Filing Dt:
|
08/25/1998
|
|
Title:
|
ADAPTIVE DATA RECOVERY SYSTEM AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09161923
|
Filing Dt:
|
09/28/1998
|
|
Title:
|
LINEARLY EXPANDABLE SELF-ROUTING CROSSBAR SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09179538
|
Filing Dt:
|
10/26/1998
|
|
Title:
|
SYSTEM AND METHOD FOR INTEGRATED DATA FLOW CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09191783
|
Filing Dt:
|
11/13/1998
|
|
Title:
|
PULSE CODE SEQUENCE ANALYZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09231101
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
GALLIUM ARSENIDE VOLTAGE-CONTROLLED OSCILLATOR AND OSCILLATOR DELAY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09246268
|
Filing Dt:
|
02/08/1999
|
|
Title:
|
COMMON-GATE TRANSIMPEDANCE AMPLIFIER WITH DYNAMICALLY CONTROLLED INPUT IMPEDANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09256426
|
Filing Dt:
|
02/23/1999
|
|
Title:
|
TRANSIMPEDANCE AMPLIFIER WITH AUTOMATIC GAIN CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09265725
|
Filing Dt:
|
03/09/1999
|
|
Title:
|
PHASE SELECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09322738
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
CONTROLLED ORTHOGONAL CURRENT OSCILLATOR WITH RANGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09345885
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
HIGH BANDWIDTH CLOCK BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09364974
|
Filing Dt:
|
07/31/1999
|
|
Title:
|
MULTIPLE-PHASE-INTERPOLATION LC VOLTAGE-CONTROLLED OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09365189
|
Filing Dt:
|
08/02/1999
|
|
Title:
|
METHOD AND APPARATUS FOR GENERATING A TIME DELAYED SIGNAL WITH A MINIMUM DATA DEPENDENCY ERROR USING AN OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09365441
|
Filing Dt:
|
08/02/1999
|
|
Title:
|
BUS ARRANGEMENTS FOR INTERCONNECTION OF DISCRETE AND/OR INTEGRATED MODULES IN A DIGITAL SYSTEM AND ASSOCIATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09376763
|
Filing Dt:
|
08/17/1999
|
|
Title:
|
MODULE BASED ADDRESS TRANSLATION ARRANGEMENT AND TRANSACTION OFFLOADING IN A DIGITAL SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09531277
|
Filing Dt:
|
03/20/2000
|
|
Title:
|
MULTIPLE CHANNEL ADAPTIVE DATA RECOVERY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
09586524
|
Filing Dt:
|
06/02/2000
|
|
Title:
|
REED-SOLOMON ENCODER AND DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09587150
|
Filing Dt:
|
06/02/2000
|
|
Title:
|
PRODUCT CODE BASED FORWARD ERROR CORRECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09592364
|
Filing Dt:
|
06/12/2000
|
|
Title:
|
Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09593264
|
Filing Dt:
|
06/13/2000
|
|
Title:
|
PULSE CODE SEQUENCE ANALYZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09594745
|
Filing Dt:
|
06/13/2000
|
|
Title:
|
MEDIA ACCESS CONTROL ARCHITECTURES AND NETWORK MANAGEMENT SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09619378
|
Filing Dt:
|
07/19/2000
|
|
Title:
|
Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09680679
|
Filing Dt:
|
10/06/2000
|
|
Title:
|
A CLOCK RECOVERY UNIT WHICH USES A DETECTED FREQUENCY DIFFERENCE SIGNAL TO HELP ESTABLISH PHASE LOCK BETWEEN A TRANSMITTED DATA SIGNAL AND A RECOVERED CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09715847
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
ACTIVELY-CONTROLLABLE OPTICAL SWITCHES BASED ON OPTICAL POSITION SENSING AND APPLICATIONS IN OPTICAL SWITCHING ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09837615
|
Filing Dt:
|
04/18/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/24/2002
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR ANGLED COAXIAL TO PLANAR STRUCTURE BROADBAND TRANSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09850530
|
Filing Dt:
|
05/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/07/2002
| | | | |
|
Title:
|
PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09865008
|
Filing Dt:
|
05/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2002
| | | | |
|
Title:
|
CLOCK BUFFER WITH DC OFFSET SUPPRESSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09870394
|
Filing Dt:
|
05/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
REDUCED GMII WITH INTERNAL TIMING COMPENSATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
09874158
|
Filing Dt:
|
06/04/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
|
Title:
|
PRODUCT CODE BASED FORWARD ERROR CORRECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
09878054
|
Filing Dt:
|
06/06/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/21/2002
| | | | |
|
Title:
|
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
09882582
|
Filing Dt:
|
06/14/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2002
| | | | |
|
Title:
|
TRANSPARENT TRANSPORT OVERHEAD MAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
09892807
|
Filing Dt:
|
06/26/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
LIMITING AMPLIFIER MODULATOR DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
09894388
|
Filing Dt:
|
06/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
|
Title:
|
OUTPUT DRIVER FOR HIGH SPEED ETHERNET TRANSCEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09955563
|
Filing Dt:
|
09/17/2001
|
|
Title:
|
PROGRAMMABLE ANALOG TAPPED DELAY LINE FILTER HAVING CASCADED DIFFERENTIAL DELAY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2005
|
Application #:
|
09956609
|
Filing Dt:
|
09/18/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
ACTUATOR-CONTROLLED MIRROR WITH Z-STOP MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09974451
|
Filing Dt:
|
10/09/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
|
Title:
|
PRECISION ON-CHIP TRANSMISSION LINE TERMINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09976511
|
Filing Dt:
|
10/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
MONOLITHIC LOSS-OF-SIGNAL DETECT CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09992743
|
Filing Dt:
|
11/14/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
LOW TEMPERATURE ALUMINUM PLANARIZATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10020491
|
Filing Dt:
|
12/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
AUTOMATIC LOAD BALANCING IN SWITCH FABRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10041888
|
Filing Dt:
|
01/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
|
Title:
|
SCALABLE CLOCK DISTRIBUTION FOR MULTIPLE CRU ON THE SAME CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10044413
|
Filing Dt:
|
10/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
LOW-DENSITY PARITY CHECK FORWARD ERROR CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10047166
|
Filing Dt:
|
01/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2002
| | | | |
|
Title:
|
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10066982
|
Filing Dt:
|
02/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/15/2002
| | | | |
|
Title:
|
RZ RECOVERY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
10074106
|
Filing Dt:
|
02/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10096442
|
Filing Dt:
|
03/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
|
Title:
|
TIME BASED PACKET SCHEDULING AND SORTING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
10096739
|
Filing Dt:
|
03/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
METHOD OF CONTROLLING THE TURN OFF CHARACTERISTICS OF A VCSEL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
10099668
|
Filing Dt:
|
03/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
HIGH BANDWIDTH CLOCK BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10119545
|
Filing Dt:
|
04/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2003
| | | | |
|
Title:
|
CLOCK AND DATA RECOVERY WITH A FEEDBACK LOOP TO ADJUST THE SLICE LEVEL OF AN INPUT SAMPLING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10138496
|
Filing Dt:
|
05/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2003
| | | | |
|
Title:
|
DATA SWITCHING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10145412
|
Filing Dt:
|
05/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
PRECISE PHASE DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10150531
|
Filing Dt:
|
05/17/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
|
Title:
|
CONTROL TECHNIQUES AND DEVICES FOR AN OPTICAL SWITCH ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
10159648
|
Filing Dt:
|
05/29/2002
|
|
Title:
|
DUAL-MIXER LOSS OF SIGNAL DETECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10189619
|
Filing Dt:
|
07/03/2002
|
|
Title:
|
TRANSFORMERLESS ETHERNET CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10222341
|
Filing Dt:
|
08/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
|
Title:
|
MULTIPLE ELEMENT CONTROLLED OPTICAL COUPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10266383
|
Filing Dt:
|
10/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/13/2003
| | | | |
|
Title:
|
MULTIPLE CHANNEL ADAPTIVE DATA RECOVERY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10282398
|
Filing Dt:
|
10/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
ADJUSTMENT OF A CLOCK DUTY CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10295276
|
Filing Dt:
|
11/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
FAST LOCKING CLOCK AND DATA RECOVERY UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10308458
|
Filing Dt:
|
12/02/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2003
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR INTER-CHIP OR CHIP-TO-SUBSTRATE CONNECTION WITH A SUB-CARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10364075
|
Filing Dt:
|
02/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
SELF-ALIGNED BIPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10411993
|
Filing Dt:
|
04/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
|
Title:
|
ON-CHIP CALIBRATED SOURCE TERMINATION FOR VOLTAGE MODE DRIVER AND METHOD OF CALIBRATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10677123
|
Filing Dt:
|
09/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10721910
|
Filing Dt:
|
11/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
METHOD OF OVERTONE SELECTION AND LEVEL CONTROL IN AN INTEGRATED CIRCUIT CMOS NEGATIVE RESISTANCE OSCILLATOR TO ACHIEVE LOW JITTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10754250
|
Filing Dt:
|
01/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2005
| | | | |
|
Title:
|
SWITCHING MODE REGULATOR FOR SFP ETHERNET ADAPTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10810271
|
Filing Dt:
|
03/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED FEC ADAPTIVE EQUALIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10852586
|
Filing Dt:
|
05/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONFIGURING THE OPERATION OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10872307
|
Filing Dt:
|
06/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT IMPLEMENTATION FOR POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11231320
|
Filing Dt:
|
09/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11330497
|
Filing Dt:
|
01/11/2006
|
|
Title:
|
DIFFERENTIAL OPTO-ELECTRONICS TRANSMITTER
|
|
