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Patent Assignment Details

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Reel/Frame:	030065/0817			Pages:	17
		Recorded:	03/20/2013
Attorney Dkt #:	TIPI 5.2-037
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 30

Patent #:	5547906	Issue Dt:	08/20/1996	Application #:	08274251	Filing Dt:	07/13/1994
Title:	METHODS FOR PRODUCING INTERGRATED CIRCUIT DEVICES

Patent #:	5716759	Issue Dt:	02/10/1998	Application #:	08602853	Filing Dt:	06/17/1996
Title:	METHOD AND APPARATUS FOR PRODUCING INTEGRATED CIRCUIT DEVICES

Patent #:	6040235	Issue Dt:	03/21/2000	Application #:	08682556	Filing Dt:	08/19/1996
Title:	METHODS AND APPARATUS FOR PRODUCING INTEGRATED CIRCUIT DEVICES

Patent #:	6022758	Issue Dt:	02/08/2000	Application #:	08765473	Filing Dt:	02/21/1997
Title:	PROCESS FOR MANUFACTURING SOLDER LEADS ON A SEMICONDUCTOR DEVICE PACKAGE

Patent #:	5980663	Issue Dt:	11/09/1999	Application #:	08952019	Filing Dt:	02/27/1998
Title:	BONDING MACHINE

Patent #:	6646289	Issue Dt:	11/11/2003	Application #:	09601895	Filing Dt:	09/22/2000
Title:	INTEGRATED CIRCUIT DEVICE

Patent #:	6777767	Issue Dt:	08/17/2004	Application #:	09725166	Filing Dt:	11/29/2000
Publication #:	US20010018236	Pub Dt:	08/30/2001
Title:	METHODS FOR PRODUCING PACKAGED INTEGRATED CIRCUIT DEVICES & PACKAGED INTEGRATED CIRCUIT DEVICES PRODUCED THEREBY

Patent #:	6624505	Issue Dt:	09/23/2003	Application #:	09758906	Filing Dt:	01/11/2001
Publication #:	US20030080398	Pub Dt:	05/01/2003
Title:	PACKAGED INTEGRATED CIRCUITS AND METHODS OF PRODUCING THEREOF

Patent #:	7144745	Issue Dt:	12/05/2006	Application #:	09922770	Filing Dt:	08/07/2001
Publication #:	US20020027296	Pub Dt:	03/07/2002
Title:	METHODS FOR PRODUCING PACKAGED INTEGRATED CIRCUIT DEVICES & PACKAGED INTEGRATED CIRCUIT DEVICES PRODUCED THEREBY

Patent #:	7033664	Issue Dt:	04/25/2006	Application #:	10277498	Filing Dt:	10/22/2002
Publication #:	US20040076797	Pub Dt:	04/22/2004
Title:	METHODS FOR PRODUCING PACKAGED INTEGRATED CIRCUIT DEVICES AND PACKAGED INTEGRATED CIRCUIT DEVICES PRODUCED THEREBY

Patent #:	7408249	Issue Dt:	08/05/2008	Application #:	10451564	Filing Dt:	05/03/2004
Publication #:	US20070013044	Pub Dt:	01/18/2007
Title:	PACKAGED INTEGRATED CIRCUITS AND METHODS OF PRODUCING THEREOF

Patent #:	6972480	Issue Dt:	12/06/2005	Application #:	10462576	Filing Dt:	06/16/2003
Publication #:	US20040251525	Pub Dt:	12/16/2004
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	7192796	Issue Dt:	03/20/2007	Application #:	10884058	Filing Dt:	07/02/2004
Publication #:	US20050104179	Pub Dt:	05/19/2005
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	7265440	Issue Dt:	09/04/2007	Application #:	11125624	Filing Dt:	05/10/2005
Publication #:	US20050205977	Pub Dt:	09/22/2005
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	7935568	Issue Dt:	05/03/2011	Application #:	11590616	Filing Dt:	10/31/2006
Publication #:	US20080099900	Pub Dt:	05/01/2008
Title:	WAFER-LEVEL FABRICATION OF LIDDED CHIPS WITH ELECTRODEPOSITED DIELECTRIC COATING

Patent #:	8604605	Issue Dt:	12/10/2013	Application #:	11650356	Filing Dt:	01/05/2007
Publication #:	US20080165519	Pub Dt:	07/10/2008
Title:	MICROELECTRONIC ASSEMBLY WITH MULTI-LAYER SUPPORT STRUCTURE

Patent #:	7495341	Issue Dt:	02/24/2009	Application #:	11699852	Filing Dt:	01/30/2007
Publication #:	US20070138498	Pub Dt:	06/21/2007
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	7807508	Issue Dt:	10/05/2010	Application #:	11789694	Filing Dt:	04/25/2007
Publication #:	US20080099907	Pub Dt:	05/01/2008
Title:	WAFER-LEVEL FABRICATION OF LIDDED CHIPS WITH ELECTRODEPOSITED DIELECTRIC COATING

Patent #:	7642629	Issue Dt:	01/05/2010	Application #:	11891867	Filing Dt:	08/13/2007
Publication #:	US20080012115	Pub Dt:	01/17/2008
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	7479398	Issue Dt:	01/20/2009	Application #:	11894473	Filing Dt:	08/21/2007
Publication #:	US20080017879	Pub Dt:	01/24/2008
Title:	METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

Patent #:	8405196	Issue Dt:	03/26/2013	Application #:	12072508	Filing Dt:	02/26/2008
Publication #:	US20080246136	Pub Dt:	10/09/2008
Title:	CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS

Patent #:	8193615	Issue Dt:	06/05/2012	Application #:	12221204	Filing Dt:	07/31/2008
Publication #:	US20090065907	Pub Dt:	03/12/2009
Title:	SEMICONDUCTOR PACKAGING PROCESS USING THROUGH SILICON VIAS

Patent #:	8310036	Issue Dt:	11/13/2012	Application #:	12784841	Filing Dt:	05/21/2010
Publication #:	US20100225006	Pub Dt:	09/09/2010
Title:	CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS

Patent #:	8735287	Issue Dt:	05/27/2014	Application #:	13488930	Filing Dt:	06/05/2012
Publication #:	US20120241976	Pub Dt:	09/27/2012
Title:	SEMICONDUCTOR PACKAGING PROCESS USING THROUGH SILICON VIAS

Patent #:	8735205	Issue Dt:	05/27/2014	Application #:	13672067	Filing Dt:	11/08/2012
Publication #:	US20130065390	Pub Dt:	03/14/2013
Title:	CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS

Assignor

Exec Dt:

03/18/2013

Assignee

2702 ORCHARD PARKWAY

SAN JOSE, CALIFORNIA USA 95134

Correspondence name and address
	DARYL K. NEFF
	LERNER, DAVID, LITTENBERG, KRUMHOLZ
	& MENTLIK, LLP
	600 SOUTH AVENUE WEST
	WESTFIELD, NJ 07090

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