Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 029048/0848 | |
| Pages: | 5 |
| | Recorded: | 09/28/2012 | | |
| Attorney Dkt #: | IBM02001 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10067411
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Filing Dt:
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02/05/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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SUPPRESSION OF LEAKAGE CURRENTS IN VLSI LOGIC AND MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10708379
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Filing Dt:
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02/27/2004
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Publication #:
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Pub Dt:
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09/01/2005
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Title:
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METHOD AND APPARATUS FOR IMPROVING CYCLE TIME IN A QUAD DATA RATE SRAM DEVICE
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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11116589
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Filing Dt:
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04/28/2005
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Title:
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METHOD AND APPARATUS FOR REDUCING SOFT ERROR RATE IN SRAM ARRAYS USING ELEVATED SRAM VOLTAGE DURING PERIODS OF LOW ACTIVITY
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Patent #:
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Issue Dt:
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12/25/2007
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Application #:
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11164556
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Filing Dt:
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11/29/2005
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Publication #:
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Pub Dt:
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05/31/2007
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Title:
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SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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11985961
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
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05/21/2009
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Title:
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CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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11998948
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Filing Dt:
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12/03/2007
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Publication #:
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Pub Dt:
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04/17/2008
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Title:
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SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
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Assignee
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| 198 CHAMPION COURT |
| SAN JOSE, CALIFORNIA 95134-1709 |
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Correspondence name and address
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CYPRESS SEMICONDUCTOR CORPORATION
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198 CHAMPION COURT
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SAN JOSE, CA 95134-1709
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