Patent Assignment Details
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| Reel/Frame: | 013890/0892 | |
| Pages: | 2 |
| | Recorded: | 08/19/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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10462031
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Filing Dt:
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06/13/2003
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Title:
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CACHING TECHNIQUE FOR ELECTRICAL SIMULATION OF VLSI INTERCONNECT
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Assignee
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| 101 INNOVATION DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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TOWNSEND AND TOWNSEND AND CREW
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J. MATTHEW ZIGMANT
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TWO EMBARCADERO CENTER, 8TH FLOOR
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SAN FRANCISCO, CA 94111-3834
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