Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 027936/0909 | |
| Pages: | 3 |
| | Recorded: | 03/26/2012 | | |
Attorney Dkt #: | INTELFOREIGHDOCS@BSTZ.COM |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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11054440
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Filing Dt:
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02/10/2005
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Publication #:
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Pub Dt:
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08/11/2005
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELLS WITH FLOATING GATES AND MEMORY CELL THRESHOLD VOLTAGE CONTROL METHOD
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13976562
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Filing Dt:
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06/27/2013
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Publication #:
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Pub Dt:
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11/07/2013
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PCT #:
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US2011054440
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Title:
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INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK
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Assignee
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2200 MISSION COLLEGE BOULEVARD |
SANTA CLARA, CALIFORNIA 95052 |
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Correspondence name and address
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VINCENT J. LESTER
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BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN, LLP
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1279 OAKMEAD PARKWAY
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SUNNYVALE, CA 94085-4040
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