|
Total properties:
85
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08279682
|
Filing Dt:
|
07/25/1994
|
|
Title:
|
FLAT-CELL ROM AND DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/1996
|
Application #:
|
08510259
|
Filing Dt:
|
08/02/1995
|
|
Title:
|
MULTISTATE PROM AND DECOMPRESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08624322
|
Filing Dt:
|
03/29/1996
|
|
Title:
|
FLEXIBLE BYTE-ERASE FLASH MEMORY AND DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08645630
|
Filing Dt:
|
05/14/1996
|
|
Title:
|
FLASH EEPROM WORLDLINE DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08664639
|
Filing Dt:
|
06/17/1996
|
|
Title:
|
FLASH MEMORY READ/WRITE CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08676066
|
Filing Dt:
|
07/05/1996
|
|
Title:
|
FLASH MEMORY WORDLINE DECODER WITH OVERERASE REPAIR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08691281
|
Filing Dt:
|
08/01/1996
|
|
Title:
|
FLASH MEMORY WITH FLEXIBLE ERASING SIZE FROM MULTI-BYTE TO MULTI-BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08726670
|
Filing Dt:
|
10/07/1996
|
|
Title:
|
FLASH MEMORY WITH DIVIDED BITLINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08745034
|
Filing Dt:
|
11/07/1996
|
|
Title:
|
BIT-REFRESHABLE METHOD AND CIRCUIT FOR REFRESHING A NONVOLATILE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08746665
|
Filing Dt:
|
11/14/1996
|
|
Title:
|
OR-PLANE MEMORY CELL ARRAY FOR FLASH MEMORY WITH BIT-BASED WRITE CAPABILITY, AND METHODS FOR PROGRAMMING AND ERASING THE MEMORY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08762707
|
Filing Dt:
|
12/09/1996
|
|
Title:
|
FLASH MEMORY WITH ROW REDUNDANCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08814913
|
Filing Dt:
|
03/11/1997
|
|
Title:
|
FREQUENCY TRIMMABLE OSCILLATOR AND FREQUENCY MULTIPLIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08819323
|
Filing Dt:
|
03/18/1997
|
|
Title:
|
FLASH MEMORY ADDRESS DECODER WITH NOVEL LATCH STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
08823571
|
Filing Dt:
|
03/25/1997
|
|
Title:
|
FLASH MEMORY ARRAY HAVING MAXIMUM THRESHOLD VOLTAGE DETECTION FOR ELIMATING OVER ERASURE PROBLEM AND ENCHANCING WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08833599
|
Filing Dt:
|
04/07/1997
|
|
Title:
|
FLASH MEMORY PROTECTION ATTRIBUTE STATUS BITS HELD IN A FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08834775
|
Filing Dt:
|
04/03/1997
|
|
Title:
|
MEMORY DEVICE WITH ON-CHIP MANUFACTURING AND MEMORY CELL DEFECT DETECTION CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08850489
|
Filing Dt:
|
05/02/1997
|
|
Title:
|
FLASH MEMORY WITH NOVEL BITLINE DECODER AND SOURCELINE LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08872475
|
Filing Dt:
|
06/05/1997
|
|
Title:
|
NOVEL FLASH MEMORY ARRAY AND DECODING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08882558
|
Filing Dt:
|
06/25/1997
|
|
Title:
|
FLASH MEMORY WITH HIGH SPEED ERASING STRUCTURE USING THIN OXIDE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08884251
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
NODE-PRECISE VOLTAGE REGULATION FOR A MOS MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08884926
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
NOVEL FLASH MEMORY ARRAY AND DECODING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08906198
|
Filing Dt:
|
08/05/1997
|
|
Title:
|
METHOD FOR PREVENTING SUB-THRESHOLD LEAKAGE IN FLASH MEMORY CELLS TO ACHIEVE ACCURATE READING, VERIFYING, AND FAST OVER-ERASED VT CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08915344
|
Filing Dt:
|
08/22/1997
|
|
Title:
|
FLASH MEMORY WITH HIGH SPEED ERASING STRUCTURE USING THIN OXIDE AND THICK OXIDE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08977194
|
Filing Dt:
|
11/24/1997
|
|
Title:
|
FLASH MEMORY HAVING LOW THRESHOLD VOLTAGE DISTRIBUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08998418
|
Filing Dt:
|
12/24/1997
|
|
Title:
|
LOW VOLTAGE, LOW CURRENT HOT-HOLE INJECTION ERASE AND HOT-ELECTRON PROGRAMMABLE FLASH MEMORY WITH ENHANCED ENDURANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09109652
|
Filing Dt:
|
07/02/1998
|
|
Title:
|
CHARGE PUMP CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09159793
|
Filing Dt:
|
09/24/1998
|
|
Title:
|
BIAS CONDITION AND X-DECODER CIRCUIT OF FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09159830
|
Filing Dt:
|
09/24/1998
|
|
Title:
|
NOVEL FLASH MEMORY ARRAY AND DECODING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09189109
|
Filing Dt:
|
11/09/1998
|
|
Title:
|
NODE-PRECISE VOLTAGE REGULATION FOR A MOS MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
09232115
|
Filing Dt:
|
01/15/1999
|
|
Title:
|
POSITIVE/NEGATIVE HIGH VOLTAGE CHARGE PUMP SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
09298032
|
Filing Dt:
|
04/22/1999
|
|
Title:
|
REVERSED SPLIT-GATE CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09351740
|
Filing Dt:
|
07/12/1999
|
|
Title:
|
REVERSED SPLIT-GATE CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09360315
|
Filing Dt:
|
07/23/1999
|
|
Title:
|
NOVEL ERASE CONDITION FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09369761
|
Filing Dt:
|
07/06/1999
|
|
Title:
|
BIAS CONDITIONS FOR REPAIR, PROGRAM AND ERASE OPERATIONS OF NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09377545
|
Filing Dt:
|
08/19/1999
|
|
Title:
|
NOVEL APPROACH TO PROVIDE HIGH EXTERNAL VOLTAGE FOR FLASH MEMORY ERASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09430060
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
FLASH MEMORY ARRAY AND DECODING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09479649
|
Filing Dt:
|
01/08/2000
|
|
Title:
|
Breakdown-Free High Voltage Input Circuitry`
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09487501
|
Filing Dt:
|
01/19/2000
|
|
Title:
|
Array Architecture And Process Flow Of Nonvolatile Memory Devices For Mass Storage Applications
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09531787
|
Filing Dt:
|
03/21/2000
|
|
Title:
|
STACKED GATE FLASH MEMORY CELL WITH REDUCED DISTURB CONDITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09680651
|
Filing Dt:
|
10/06/2000
|
|
Title:
|
Multiple level flash memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09693503
|
Filing Dt:
|
10/23/2000
|
|
Title:
|
Novel approach to provide high external voltage for flash memory erase
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09696085
|
Filing Dt:
|
10/26/2000
|
|
Title:
|
A NON-VOLATILE SEMICONDUCTOR MEMORY HAVING SPLIT-GATE MEMORY CELLS MIRRORED IN A VIRTUAL GROUND CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09852247
|
Filing Dt:
|
05/09/2001
|
|
Title:
|
NOVEL 3-STEP WRITE OPERATION NONVOLATILE SEMICONDUCTOR ONE-TRANSISTOR, NOR-TYPE FLASH EEPROM MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09940159
|
Filing Dt:
|
08/27/2001
|
|
Title:
|
THREE STEP WRITE PROCESS USED FOR A NONVOLATILE NOR TYPE EEPROM MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09978230
|
Filing Dt:
|
10/16/2001
|
|
Title:
|
NOVEL SET OF THREE LEVEL CONCURRENT WORD LINE BIAS CONDITIONS FOR A NOR TYPE FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10016898
|
Filing Dt:
|
12/14/2001
|
|
Title:
|
TWO TRANSISTOR FLASH MEMORY CELL FOR USE IN EEPROM ARRAYS WITH A PROGRAMMABLE LOGIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10076826
|
Filing Dt:
|
02/15/2002
|
|
Title:
|
BIT-BY-BIT VT-CORRECTION OPERATION FOR NONVOLATILE SEMICONDUCTOR ONE-TRANSISTOR CELL, NOR-TYPE FLASH EEPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
10090356
|
Filing Dt:
|
03/04/2002
|
|
Title:
|
NOVEL METHOD TO TURN A FLASH MEMORY INTO A VERSATILE, LOW-COST MULTIPLE TIME PROGRAMMABLE EPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
10104736
|
Filing Dt:
|
03/22/2002
|
|
Title:
|
NOVEL CIRCUIT DESIGN FOR ACCEPTING MULTIPLE INPUT VOLTAGES FOR FLASH EEPROM MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
10131271
|
Filing Dt:
|
04/23/2002
|
|
Title:
|
NOVEL FLASH MEMORY ARRAY STRUCTURE SUITABLE FOR MULTIPLE SIMULTANEOUS OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10170492
|
Filing Dt:
|
06/13/2002
|
|
Title:
|
NOVEL EEPROM CELL STRUCTURE AND ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
10191228
|
Filing Dt:
|
07/09/2002
|
|
Title:
|
NOVEL FLASH MEMORY ARRAY FOR MULTIPLE SIMULTANEOUS OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10223208
|
Filing Dt:
|
08/19/2002
|
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10233642
|
Filing Dt:
|
09/03/2002
|
|
Title:
|
NOVEL PARALLEL CHANNEL PROGRAMMING SCHEME FOR MLC FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10351179
|
Filing Dt:
|
01/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
COMBINATION NONVOLATILE MEMORY USING UNIFIED TECHNOLOGY WITH BYTE, PAGE AND BLOCK WRITE AND SIMULTANEOUS READ AND WRITE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10351180
|
Filing Dt:
|
01/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10353584
|
Filing Dt:
|
01/29/2003
|
|
Title:
|
NOVEL HIGHLY-INTEGRATED FLASH MEMORY AND MASK ROM ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10364033
|
Filing Dt:
|
02/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
|
Title:
|
NOVEL HIGHLY-INTEGRATED FLASH MEMORY AND MASK ROM ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10423558
|
Filing Dt:
|
04/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
NOVEL FLASH MEMORY ARRAY STRUCTURE SUITABLE FOR MULTIPLE SIMULTANEOUS OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
10423559
|
Filing Dt:
|
04/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
NOVEL FLASH MEMORY ARRAY STRUCTURE SUITABLE FOR MULTIPLE SIMULTANEOUS OPERATIONS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10616751
|
Filing Dt:
|
07/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
Stacked gate flash memory cell with reduced disturb conditions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10627183
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
NOVEL SET OF THREE LEVEL CONCURRENT WORD LINE BIAS CONDITIONS FOR A NOR TYPE FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10627834
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
NOVEL SET OF THREE LEVEL CONCURRENT WORD LINE BIAS CONDITIONS FOR A NOR TYPE FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10790578
|
Filing Dt:
|
03/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
ARRAY ARCHITECTURE AND PROCESS FLOW OF NONVOLATILE MEMORY DEVICES FOR MASS STORAGE APPLICATIONS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10790579
|
Filing Dt:
|
03/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
A NON-VOLATILE SEMICONDUCTOR MEMORY HAVING SPLIT-GATE MEMORY CELLS MIRRORED IN A VIRTUAL GROUND CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
11011304
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
COMBINATION NONVOLATILE MEMORY USING UNIFIED TECHNOLOGY WITH BYTE, PAGE AND BLOCK WRITE AND SIMULTANEOUS READ AND WRITE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11011306
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
COMBINATION NONVOLATILE MEMORY USING UNIFIED TECHNOLOGY WITH BYTE, PAGE AND BLOCK WRITE AND SIMULTANEOUS READ AND WRITE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
11025822
|
Filing Dt:
|
12/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
|
Title:
|
NOVEL COMBINATION NONVOLATILE INTEGRATED MEMORY SYSTEM USING A UNIVERSAL TECHNOLOGY MOST SUITABLE FOR HIGH-DENSITY, HIGH-FLEXIBILITY AND HIGH-SECURITY SIM-CARD, SMART-CARD AND E-PASSPORT APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
11036835
|
Filing Dt:
|
01/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
11036868
|
Filing Dt:
|
01/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
11036945
|
Filing Dt:
|
01/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11036961
|
Filing Dt:
|
01/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
11040862
|
Filing Dt:
|
01/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
|
Title:
|
UNIFIED NON-VOLATILE MEMORY DEVICE AND METHOD FOR INTEGRATING NOR AND NAND-TYPE FLASH MEMORY AND EEPROM DEVICE ON A SINGLE SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
11056901
|
Filing Dt:
|
02/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
NOVEL NVRAM MEMORY CELL ARCHITECTURE THAT INTEGRATES CONVENTIONAL SRAM AND FLASH CELLS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11091098
|
Filing Dt:
|
03/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
Novel EEPROM cell structure and array architecture
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11305700
|
Filing Dt:
|
12/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
NOVEL COMBO MEMORY DESIGN AND TECHNOLOGY FOR MULTIPLE-FUNCTION JAVA CARD, SIM-CARD, BIO-PASSPORT AND BIO-ID CARD APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11376076
|
Filing Dt:
|
03/15/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11391170
|
Filing Dt:
|
03/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11391507
|
Filing Dt:
|
03/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11391662
|
Filing Dt:
|
03/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11442379
|
Filing Dt:
|
05/26/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
|
Title:
|
NOVEL MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
11483241
|
Filing Dt:
|
07/07/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11633326
|
Filing Dt:
|
12/04/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
|
Title:
|
COMBINATION NONVOLATILE MEMORY USING UNIFIED TECHNOLOGY WITH BYTE, PAGE AND BLOCK WRITE AND SIMULTANEOUS READ AND WRITE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11633334
|
Filing Dt:
|
12/04/2006
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
|
Title:
|
COMBINATION NONVOLATILE MEMORY USING UNIFIED TECHNOLOGY WITH BYTE, PAGE AND BLOCK WRITE AND SIMULTANEOUS READ AND WRITE OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12001647
|
Filing Dt:
|
12/12/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
|
Title:
|
NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE
|
|
