Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 039492/0956 | |
| Pages: | 5 |
| | Recorded: | 07/27/2016 | | |
| Attorney Dkt #: | 70027 |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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06/02/2015
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Application #:
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12709425
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Filing Dt:
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02/19/2010
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Publication #:
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Pub Dt:
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06/17/2010
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13589018
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Filing Dt:
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08/17/2012
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Publication #:
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Pub Dt:
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12/06/2012
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Title:
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EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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09/22/2015
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Application #:
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14219463
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Filing Dt:
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03/19/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/24/2016
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Application #:
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14231526
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Filing Dt:
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03/31/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING
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Patent #:
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Issue Dt:
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04/05/2016
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Application #:
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14254584
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Filing Dt:
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04/16/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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14282598
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Filing Dt:
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05/20/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED LASER VIA INTERPOSER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/29/2016
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Application #:
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14285601
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Filing Dt:
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05/22/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/31/2016
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Application #:
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14791287
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Filing Dt:
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07/03/2015
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Publication #:
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Pub Dt:
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10/29/2015
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF
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Assignee
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| 10 ANG MO KIO STREET 65 |
| #04-08/09 TECHPOINT |
| SINGAPORE, SINGAPORE 569059 |
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Correspondence name and address
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WONG & REES LLP
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4677 OLD IRONSIDES DRIVE
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SUITE 370
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SANTA CLARA, CA 95054
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