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Reel/Frame:064760/0986   Pages: 13
Recorded: 08/30/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319)
Total properties: 89
1
Patent #:
7381634
Issue Dt:
06/03/2008
Application #:
10907732
Filing Dt:
04/13/2005
Publication #:
US20060231948
Pub Dt:
10/19/2006
Title:
INTEGRATED CIRCUIT SYSTEM FOR BONDING
2
Patent #:
7338841
Issue Dt:
03/04/2008
Application #:
10907758
Filing Dt:
04/14/2005
Publication #:
US20060234426
Pub Dt:
10/19/2006
Title:
LEADFRAME WITH ENCAPSULANT GUIDE AND METHOD FOR THE FABRICATION THEREOF
3
Patent #:
7410824
Issue Dt:
08/12/2008
Application #:
11009436
Filing Dt:
12/09/2004
Publication #:
US20060125110
Pub Dt:
06/15/2006
Title:
METHOD FOR SOLDER BUMPING, AND SOLDER-BUMPING STRUCTURES PRODUCED THEREBY
4
Patent #:
7554179
Issue Dt:
06/30/2009
Application #:
11053564
Filing Dt:
02/07/2005
Publication #:
US20060175689
Pub Dt:
08/10/2006
Title:
MULTI-LEADFRAME SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
5
Patent #:
7298026
Issue Dt:
11/20/2007
Application #:
11126052
Filing Dt:
05/09/2005
Publication #:
US20060249830
Pub Dt:
11/09/2006
Title:
LARGE DIE PACKAGE AND METHOD FOR THE FABRICATION THEREOF
6
Patent #:
7445955
Issue Dt:
11/04/2008
Application #:
11160837
Filing Dt:
07/12/2005
Publication #:
US20060043560
Pub Dt:
03/02/2006
Title:
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
7
Patent #:
7566650
Issue Dt:
07/28/2009
Application #:
11162822
Filing Dt:
09/23/2005
Publication #:
US20070069346
Pub Dt:
03/29/2007
Title:
INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM
8
Patent #:
7517729
Issue Dt:
04/14/2009
Application #:
11163559
Filing Dt:
10/22/2005
Publication #:
US20060103009
Pub Dt:
05/18/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
9
Patent #:
7388280
Issue Dt:
06/17/2008
Application #:
11163770
Filing Dt:
10/29/2005
Publication #:
US20060186514
Pub Dt:
08/24/2006
Title:
PACKAGE STACKING LEAD FRAME SYSTEM
10
Patent #:
7622325
Issue Dt:
11/24/2009
Application #:
11163771
Filing Dt:
10/29/2005
Publication #:
US20070096282
Pub Dt:
05/03/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HIGH-DENSITY SMALL FOOTPRINT SYSTEM-IN-PACKAGE
11
Patent #:
7443018
Issue Dt:
10/28/2008
Application #:
11164087
Filing Dt:
11/09/2005
Publication #:
US20070108601
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING RIBBON BOND INTERCONNECT
12
Patent #:
7420265
Issue Dt:
09/02/2008
Application #:
11164321
Filing Dt:
11/17/2005
Publication #:
US20070108559
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATED CIRCUIT SUPPORT
13
Patent #:
7598606
Issue Dt:
10/06/2009
Application #:
11164453
Filing Dt:
11/22/2005
Publication #:
US20060197207
Pub Dt:
09/07/2006
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
14
Patent #:
7378300
Issue Dt:
05/27/2008
Application #:
11234528
Filing Dt:
09/22/2005
Publication #:
US20070080437
Pub Dt:
04/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
15
Patent #:
7598599
Issue Dt:
10/06/2009
Application #:
11276681
Filing Dt:
03/09/2006
Publication #:
US20070210422
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
16
Patent #:
7368319
Issue Dt:
05/06/2008
Application #:
11276940
Filing Dt:
03/17/2006
Publication #:
US20070218689
Pub Dt:
09/20/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
17
Patent #:
7501697
Issue Dt:
03/10/2009
Application #:
11276946
Filing Dt:
03/17/2006
Publication #:
US20070216010
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
18
Patent #:
7521297
Issue Dt:
04/21/2009
Application #:
11276948
Filing Dt:
03/17/2006
Publication #:
US20070216007
Pub Dt:
09/20/2007
Title:
MULTICHIP PACKAGE SYSTEM
19
Patent #:
7304859
Issue Dt:
12/04/2007
Application #:
11277973
Filing Dt:
03/30/2006
Publication #:
US20070236900
Pub Dt:
10/11/2007
Title:
CHIP CARRIER AND FABRICATION METHOD
20
Patent #:
7521781
Issue Dt:
04/21/2009
Application #:
11278343
Filing Dt:
03/31/2006
Publication #:
US20070108589
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD CLAMP LINE CRITICAL AREA HAVING WIDENED CONDUCTIVE TRACES
21
Patent #:
7443037
Issue Dt:
10/28/2008
Application #:
11278421
Filing Dt:
04/01/2006
Publication #:
US20070229107
Pub Dt:
10/04/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONNECTION PROTECTION
22
Patent #:
7445962
Issue Dt:
11/04/2008
Application #:
11306148
Filing Dt:
12/16/2005
Publication #:
US20060197209
Pub Dt:
09/07/2006
Title:
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH DENSE ROUTABILITY AND HIGH THERMAL CONDUCTIVITY
23
Patent #:
7456088
Issue Dt:
11/25/2008
Application #:
11306627
Filing Dt:
01/04/2006
Publication #:
US20070158833
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE
24
Patent #:
7364945
Issue Dt:
04/29/2008
Application #:
11306628
Filing Dt:
01/04/2006
Publication #:
US20060220256
Pub Dt:
10/05/2006
Title:
METHOD OF MOUNTING AN INTEGRATED CIRCUIT PACKAGE IN AN ENCAPSULANT CAVITY
25
Patent #:
7365417
Issue Dt:
04/29/2008
Application #:
11306693
Filing Dt:
01/06/2006
Publication #:
US20070158792
Pub Dt:
07/12/2007
Title:
OVERHANG INTEGRATED CIRCUIT PACKAGE SYSTEM
26
Patent #:
7446396
Issue Dt:
11/04/2008
Application #:
11306805
Filing Dt:
01/11/2006
Publication #:
US20070108604
Pub Dt:
05/17/2007
Title:
STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
27
Patent #:
7323774
Issue Dt:
01/29/2008
Application #:
11306808
Filing Dt:
01/11/2006
Publication #:
US20070158820
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PEDESTAL STRUCTURE
28
Patent #:
7598600
Issue Dt:
10/06/2009
Application #:
11307247
Filing Dt:
01/27/2006
Publication #:
US20070108560
Pub Dt:
05/17/2007
Title:
STACKABLE POWER SEMICONDUCTOR PACKAGE SYSTEM
29
Patent #:
7557432
Issue Dt:
07/07/2009
Application #:
11307285
Filing Dt:
01/31/2006
Publication #:
US20070108564
Pub Dt:
05/17/2007
Title:
THERMALLY ENHANCED POWER SEMICONDUCTOR PACKAGE SYSTEM
30
Patent #:
7615851
Issue Dt:
11/10/2009
Application #:
11307313
Filing Dt:
01/31/2006
Publication #:
US20070111394
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
31
Patent #:
7298052
Issue Dt:
11/20/2007
Application #:
11307314
Filing Dt:
01/31/2006
Publication #:
US20070111389
Pub Dt:
05/17/2007
Title:
MICRO CHIP-SCALE-PACKAGE SYSTEM
32
Patent #:
7485502
Issue Dt:
02/03/2009
Application #:
11307315
Filing Dt:
01/31/2006
Publication #:
US20070176285
Pub Dt:
08/02/2007
Title:
INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
33
Patent #:
7309622
Issue Dt:
12/18/2007
Application #:
11307350
Filing Dt:
02/01/2006
Publication #:
US20070111397
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
34
Patent #:
7414310
Issue Dt:
08/19/2008
Application #:
11307363
Filing Dt:
02/02/2006
Publication #:
US20070176280
Pub Dt:
08/02/2007
Title:
WAFERSCALE PACKAGE SYSTEM
35
Patent #:
7541221
Issue Dt:
06/02/2009
Application #:
11307386
Filing Dt:
02/04/2006
Publication #:
US20070181982
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT
36
Patent #:
7435619
Issue Dt:
10/14/2008
Application #:
11307615
Filing Dt:
02/14/2006
Publication #:
US20070187826
Pub Dt:
08/16/2007
Title:
METHOD OF FABRICATING A 3-D PACKAGE STACKING SYSTEM
37
Patent #:
7400049
Issue Dt:
07/15/2008
Application #:
11307683
Filing Dt:
02/16/2006
Publication #:
US20070187839
Pub Dt:
08/16/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
38
Patent #:
7298037
Issue Dt:
11/20/2007
Application #:
11307722
Filing Dt:
02/17/2006
Publication #:
US20070194423
Pub Dt:
08/23/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH RECESSED SPACER
39
Patent #:
7298038
Issue Dt:
11/20/2007
Application #:
11307861
Filing Dt:
02/25/2006
Publication #:
US20070200205
Pub Dt:
08/30/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
40
Patent #:
7385299
Issue Dt:
06/10/2008
Application #:
11307862
Filing Dt:
02/25/2006
Publication #:
US20070200257
Pub Dt:
08/30/2007
Title:
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE
41
Patent #:
7312519
Issue Dt:
12/25/2007
Application #:
11331564
Filing Dt:
01/12/2006
Publication #:
US20070158810
Pub Dt:
07/12/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
42
Patent #:
7449369
Issue Dt:
11/11/2008
Application #:
11338328
Filing Dt:
01/23/2006
Publication #:
US20070170554
Pub Dt:
07/26/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
43
Patent #:
7521780
Issue Dt:
04/21/2009
Application #:
11354694
Filing Dt:
02/14/2006
Publication #:
US20070108597
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT DISSIPATION ENCLOSURE
44
Patent #:
7420269
Issue Dt:
09/02/2008
Application #:
11379097
Filing Dt:
04/18/2006
Publication #:
US20070241442
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
45
Patent #:
7498667
Issue Dt:
03/03/2009
Application #:
11379106
Filing Dt:
04/18/2006
Publication #:
US20070241453
Pub Dt:
10/18/2007
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
46
Patent #:
7354800
Issue Dt:
04/08/2008
Application #:
11380596
Filing Dt:
04/27/2006
Publication #:
US20060244157
Pub Dt:
11/02/2006
Title:
METHOD OF FABRICATING A STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
47
Patent #:
7498665
Issue Dt:
03/03/2009
Application #:
11381726
Filing Dt:
05/04/2006
Publication #:
US20070108567
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
48
Patent #:
7443015
Issue Dt:
10/28/2008
Application #:
11381734
Filing Dt:
05/04/2006
Publication #:
US20070108624
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
49
Patent #:
7495325
Issue Dt:
02/24/2009
Application #:
11381827
Filing Dt:
05/05/2006
Publication #:
US20060266938
Pub Dt:
11/30/2006
Title:
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
50
Patent #:
7582960
Issue Dt:
09/01/2009
Application #:
11381901
Filing Dt:
05/05/2006
Publication #:
US20060249851
Pub Dt:
11/09/2006
Title:
MULTIPLE CHIP PACKAGE MODULE INCLUDING DIE STACKED OVER ENCAPSULATED PACKAGE
51
Patent #:
7482683
Issue Dt:
01/27/2009
Application #:
11383038
Filing Dt:
05/12/2006
Publication #:
US20070262423
Pub Dt:
11/15/2007
Title:
INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
52
Patent #:
7518224
Issue Dt:
04/14/2009
Application #:
11383403
Filing Dt:
05/15/2006
Publication #:
US20070108581
Pub Dt:
05/17/2007
Title:
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
53
Patent #:
7545031
Issue Dt:
06/09/2009
Application #:
11394363
Filing Dt:
03/30/2006
Publication #:
US20060226528
Pub Dt:
10/12/2006
Title:
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
54
Patent #:
7429786
Issue Dt:
09/30/2008
Application #:
11394635
Filing Dt:
03/31/2006
Publication #:
US20060244117
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR PACKAGE INCLUDING SECOND SUBSTRATE AND HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
55
Patent #:
7372141
Issue Dt:
05/13/2008
Application #:
11395529
Filing Dt:
03/31/2006
Publication #:
US20060220209
Pub Dt:
10/05/2006
Title:
SEMICONDUCTOR STACKED PACKAGE ASSEMBLY HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
56
Patent #:
7589407
Issue Dt:
09/15/2009
Application #:
11396954
Filing Dt:
04/03/2006
Publication #:
US20060226536
Pub Dt:
10/12/2006
Title:
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
57
Patent #:
7429787
Issue Dt:
09/30/2008
Application #:
11397027
Filing Dt:
03/31/2006
Publication #:
US20060220210
Pub Dt:
10/05/2006
Title:
SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SURFACES ON UPPER AND LOWER SIDES
58
Patent #:
7528474
Issue Dt:
05/05/2009
Application #:
11420873
Filing Dt:
05/30/2006
Publication #:
US20060267175
Pub Dt:
11/30/2006
Title:
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
59
Patent #:
7550680
Issue Dt:
06/23/2009
Application #:
11424202
Filing Dt:
06/14/2006
Publication #:
US20070289777
Pub Dt:
12/20/2007
Title:
PACKAGE-ON-PACKAGE SYSTEM
60
Patent #:
7394148
Issue Dt:
07/01/2008
Application #:
11424480
Filing Dt:
06/15/2006
Publication #:
US20060284299
Pub Dt:
12/21/2006
Title:
MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES
61
Patent #:
7556987
Issue Dt:
07/07/2009
Application #:
11428272
Filing Dt:
06/30/2006
Publication #:
US20080001263
Pub Dt:
01/03/2008
Title:
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ETCHED RING AND DIE PADDLE
62
Patent #:
7563647
Issue Dt:
07/21/2009
Application #:
11456532
Filing Dt:
07/10/2006
Publication #:
US20070108569
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT
63
Patent #:
7545032
Issue Dt:
06/09/2009
Application #:
11456544
Filing Dt:
07/10/2006
Publication #:
US20080006926
Pub Dt:
01/10/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STIFFENER
64
Patent #:
7399658
Issue Dt:
07/15/2008
Application #:
11459317
Filing Dt:
07/21/2006
Publication #:
US20070111379
Pub Dt:
05/17/2007
Title:
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
65
Patent #:
7495321
Issue Dt:
02/24/2009
Application #:
11459557
Filing Dt:
07/24/2006
Publication #:
US20080017994
Pub Dt:
01/24/2008
Title:
LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE
66
Patent #:
7535086
Issue Dt:
05/19/2009
Application #:
11462320
Filing Dt:
08/03/2006
Publication #:
US20080029858
Pub Dt:
02/07/2008
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
67
Patent #:
7439620
Issue Dt:
10/21/2008
Application #:
11462537
Filing Dt:
08/04/2006
Publication #:
US20080029905
Pub Dt:
02/07/2008
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
68
Patent #:
7618848
Issue Dt:
11/17/2009
Application #:
11463505
Filing Dt:
08/09/2006
Publication #:
US20080036052
Pub Dt:
02/14/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE
69
Patent #:
7541222
Issue Dt:
06/02/2009
Application #:
11530802
Filing Dt:
09/11/2006
Publication #:
US20070063354
Pub Dt:
03/22/2007
Title:
WIRE SWEEP RESISTANT SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
70
Patent #:
7582957
Issue Dt:
09/01/2009
Application #:
11558404
Filing Dt:
11/09/2006
Publication #:
US20080111218
Pub Dt:
05/15/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
71
Patent #:
7479692
Issue Dt:
01/20/2009
Application #:
11558413
Filing Dt:
11/09/2006
Publication #:
US20080111217
Pub Dt:
05/15/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
72
Patent #:
7352055
Issue Dt:
04/01/2008
Application #:
11562957
Filing Dt:
11/22/2006
Publication #:
US20070090537
Pub Dt:
04/26/2007
Title:
SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING
73
Patent #:
7479409
Issue Dt:
01/20/2009
Application #:
11610304
Filing Dt:
12/13/2006
Publication #:
US20080142934
Pub Dt:
06/19/2008
Title:
INTEGRATED CIRCUIT PACKAGE WITH ELEVATED EDGE LEADFRAME
74
Patent #:
7537962
Issue Dt:
05/26/2009
Application #:
11615922
Filing Dt:
12/22/2006
Publication #:
US20080150093
Pub Dt:
06/26/2008
Title:
METHOD OF FABRICATING A SHIELDED STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
75
Patent #:
7518226
Issue Dt:
04/14/2009
Application #:
11671684
Filing Dt:
02/06/2007
Publication #:
US20080185719
Pub Dt:
08/07/2008
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
76
Patent #:
7517733
Issue Dt:
04/14/2009
Application #:
11689645
Filing Dt:
03/22/2007
Publication #:
US20080230876
Pub Dt:
09/25/2008
Title:
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
77
Patent #:
7429798
Issue Dt:
09/30/2008
Application #:
11690703
Filing Dt:
03/23/2007
Publication #:
US20070158813
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
78
Patent #:
7569421
Issue Dt:
08/04/2009
Application #:
11744657
Filing Dt:
05/04/2007
Publication #:
US20080272476
Pub Dt:
11/06/2008
Title:
THROUGH-HOLE VIA ON SAW STREETS
79
Patent #:
7615865
Issue Dt:
11/10/2009
Application #:
11751440
Filing Dt:
05/21/2007
Publication #:
US20080293232
Pub Dt:
11/27/2008
Title:
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
80
Patent #:
7553752
Issue Dt:
06/30/2009
Application #:
11765930
Filing Dt:
06/20/2007
Publication #:
US20080315372
Pub Dt:
12/25/2008
Title:
METHOD OF MAKING A WAFER LEVEL INTEGRATION PACKAGE
81
Patent #:
7414318
Issue Dt:
08/19/2008
Application #:
11766095
Filing Dt:
06/20/2007
Publication #:
US20070241432
Pub Dt:
10/18/2007
Title:
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
82
Patent #:
7566966
Issue Dt:
07/28/2009
Application #:
11850197
Filing Dt:
09/05/2007
Publication #:
US20090057863
Pub Dt:
03/05/2009
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE
83
Patent #:
7585750
Issue Dt:
09/08/2009
Application #:
11861233
Filing Dt:
09/25/2007
Publication #:
US20080274603
Pub Dt:
11/06/2008
Title:
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIA ON SAW STREETS FORMED WITH PARTIAL SAW
84
Patent #:
7619314
Issue Dt:
11/17/2009
Application #:
11869738
Filing Dt:
10/09/2007
Publication #:
US20080029862
Pub Dt:
02/07/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
85
Patent #:
7525812
Issue Dt:
04/28/2009
Application #:
11877613
Filing Dt:
10/23/2007
Publication #:
US20080043450
Pub Dt:
02/21/2008
Title:
CHIP CARRIER AND FABRICATION METHOD
86
Patent #:
7576414
Issue Dt:
08/18/2009
Application #:
11934654
Filing Dt:
11/02/2007
Publication #:
US20090117729
Pub Dt:
05/07/2009
Title:
ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE
87
Patent #:
7482203
Issue Dt:
01/27/2009
Application #:
12005499
Filing Dt:
12/26/2007
Publication #:
US20080105965
Pub Dt:
05/08/2008
Title:
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
88
Patent #:
7618846
Issue Dt:
11/17/2009
Application #:
12140092
Filing Dt:
06/16/2008
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
89
Patent #:
10777528
Issue Dt:
09/15/2020
Application #:
15615693
Filing Dt:
06/06/2017
Publication #:
US20170271305
Pub Dt:
09/21/2017
Title:
Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
Assignor
1
STATS CHIPPAC PTE. LTE.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE 768442
Correspondence name and address
SEAN WOODEN
1919 PENNSYLVANIA AVE., SUITE 800
WASHINGTON, DC 20006

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