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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
08/16/2022
Application #:
17327659
Filing Dt:
05/21/2021
Inventors:
Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes et al
Title:
MAJORITY LOGIC GATE HAVING PARAELECTRIC INPUT CAPACITORS AND A LOCAL CONDITIONING MECHANISM
Assignment: 1
Reel/Frame:
057870/0328Recorded: 10/21/2021Pages: 14
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
08/29/2021
Exec Dt:
06/06/2021
Exec Dt:
06/04/2021
Exec Dt:
06/08/2021
Exec Dt:
07/26/2021
Exec Dt:
07/27/2021
Exec Dt:
06/06/2021
Assignee:
180 STEUART STREET
#19254
SAN FRANCISCO, CALIFORNIA 94105
Correspondent:
MUGHAL IP P.C.
1500 NW BETHANY BLVD.
SUITE 200
BEAVERTON, OR 97006
Assignment: 2
Reel/Frame:
059333/0616Recorded: 03/07/2022Pages: 15
Conveyance:
CORRECTIVE ASSIGNMENT TO CORRECT THE LAST NAME OF FIRST INVENTOR PREVIOUSLY RECORDED AT REEL: 057870 FRAME: 0328. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Assignors:
Exec Dt:
08/29/2021
Exec Dt:
06/06/2021
Exec Dt:
06/04/2021
Exec Dt:
06/08/2021
Exec Dt:
07/26/2021
Exec Dt:
07/27/2021
Exec Dt:
06/06/2021
Assignee:
180 STEUART STREET
#19254
SAN FRANCISCO, CALIFORNIA 94105
Correspondent:
MUGHAL IP P.C.
1500 NW BETHANY BLVD.
SUITE 200
BEAVERTON, OR 97006

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