Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/28/1997
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Application #:
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08618445
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Filing Dt:
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03/19/1996
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Inventors:
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DANESH TAVANA, WILSON K. YEE, VICTOR A. HOLEN
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Title:
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FPGA ARCHITECTURE WITH REPEATABLE TILES INCLUDING ROUTING MATRICES AND LOGIC MATRICES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2100 LOGIC DRIVE |
| SAN JOSE, CALIFORNIA 95124 |
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| XILINX, INC. |
| 2100 LOGIC DR |
| ATTN: LEGAL DEPT |
| SAN JOSE, CA 95124 |
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