Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/09/1998
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Application #:
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08650084
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Filing Dt:
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05/17/1996
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Inventors:
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DEAN C. BULLOCK, SUDHINDAR BALAKRISHNA
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Title:
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BIT ERROR RATE DETECTION SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2975 STENDER WAY |
| SANTA CLARA, CALIFORNIA 95054 |
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| FLIESLER, DUBB, MEYER AND LOVEJOY |
| LARRY E. VIERRA, ESQ. |
| FOUR EMBARCADERO CENTER |
| FOURTH FLOOR |
| SAN FRANCISCO, CA 94111 |
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