Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08744082
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Filing Dt:
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11/04/1996
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Inventors:
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YOSHIRO NAKATA, SHIN HASHIMOTO, ISAO MIYANAGA
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING FAILURE DETECTION CIRCUITRY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| C/O SAKURA SOGO JIMUSHO |
| 1-11 KANDA-JINBOCHO, CHIYODA-KU |
| TOKYO, JAPAN |
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| SUGHRUE MION, PLLC |
| 2100 PENNSYLVANIA AVE. NW |
| SUITE 800 |
| WASHINGTON, DC 20037-3213 |
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