Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08545388
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Filing Dt:
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10/19/1995
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Inventor:
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YIH-SHUNG LIN
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Title:
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INTEGRATED CIRCUIT WITH PLANARIZED DIELECTRIC LAYER BETWEEN SUCCESSIVE POLYSILICON LAYERS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| M/S 2346 |
| 1310 ELECTRONICS DRIVE |
| CARROLLTON, TEXAS 75006 |
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| LISA K. JORGENSON |
| M/S 2348 |
| 1310 ELECTRONICS DRIVE |
| CARROLLTON, TX 75006-5039 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| M/S 2346 |
| 1310 ELECTRONICS DR. |
| CARROLLTON, TEXAS 75006 |
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| LISA K. JORGENSON |
| 1310 ELECTRONICS DR., M/S 2346 |
| CARROLLTON, TX 75006-5039 |
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