Patent Assignment Abstract of Title
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Total Assignments:
6
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09120031
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Filing Dt:
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07/21/1998
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Inventors:
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AIKO NISHINO, HISASHI IWAMOTO
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Title:
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OUTPUT CIRCUIT AND SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING A FUNCTION OF PREVENTING OUTPUT OF INVALID DATA
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 99 CANAL CENTER PLAZA, SUITE 300 |
| ALEXANDRIA, VA 22314 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT RE-RECORD OF INSTRUMENT PREVIOUSLY RECORDED ON REEL 9336, FRAME 0747 TO INCLUDE BOTH ASSIGNEES.
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| 6-2, OOTEMACHI 2-CHOME, CHIYODA-KU |
| TOKYO100-0004, JAPAN |
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| MCDERMOTT, WILL & EMERY |
| STEPHEN A. BECKER |
| 600 13TH STREET, N.W. |
| WASHINGTON DC 20005 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN 211-8668 |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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Assignment:
4
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| 2-24, TOYOSU 3-CHOME, KOUTOU-KU |
| TOKYO, JAPAN |
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| MATTINGLY & MALUR, PC |
| 1800 DIAGONAL ROAD |
| SUITE 210 |
| ALEXANDRIA, VA 22314 |
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Assignment:
5
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 5-20-1 JOSUIHON-CHO, KODAIRA |
| TOKYO, JAPAN 187-8588 |
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| TOMOKI TANIDA |
| MCDERMOTT WILL & EMERY LLP |
| 500 NORTH CAPITOL STREET, N.W. |
| WASHINGTON, DC 20001 |
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Assignment:
6
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MERGER (SEE DOCUMENT FOR DETAILS).
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| 2-24, TOYOSU 3-CHOME, KOUTOU-KU |
| TOKYO, JAPAN |
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| MATTINGLY & MALUR, PC |
| 1800 DIAGONAL ROAD |
| SUITE 210 |
| ALEXANDRIA, VA 22314 |
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