Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10271176
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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04/24/2003
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Inventor:
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Toshiyuki Makita
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Title:
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SEMICONDUCTOR FABRICATING METHOD EMPLOYING PARALLEL PROCESSING AND INSPECTION TECHNIQUES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-35 KITASHINAGAWA 6-CHOME, SHINAGAWA-KU |
| TOKYO, JAPAN |
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| HOLLAND & KNIGHT LLP |
| ROBERT J. DEPKE |
| 55 WEST MONROE STREET |
| SUITE 800 |
| CHICAGO, IL 60603 |
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Assignment:
2
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INTELLECTUAL PROPERTY SECURITY AGREEMENT (FIRST LIEN)
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| 601 108TH AVENUE N.E., 5TH FLOOR |
| BELLEVUE, WASHINGTON 98004 |
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| MARK E. ASHTON / SCHIFF HARDIN LLP |
| 6600 SEARS TOWER |
| CHICAGO, IL 60606 |
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Assignment:
3
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RELEASE OF INTELLECTUAL PROPERTY SECURITY AGREEMENT AT REEL 018303 FRAME 0390
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| 1650 TECHNOLOGY DRIVE, SUITE 700 |
| SAN JOSE, CALIFORNIA 95110 |
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| LATHAM & WATKINS LLP |
| 650 TOWN CENTER DRIVE, 20TH FLOOR |
| COSTA MESA, CA 92626 |
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