Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11190509
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Filing Dt:
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07/26/2005
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Publication #:
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Pub Dt:
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02/02/2006
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Inventors:
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Ashish Kumar Goel, Davinder Aggarwal
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Title:
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FPGA-BASED DIGITAL CIRCUIT FOR REDUCING READBACK TIME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| PLOT NO. 2, 3 & 18, SECTOR 16A |
| INSTITUTIONAL AREA, NOIDA-201 301 |
| UTTAR PRADESH, INDIA |
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| HOGAN & HARTSON LLP |
| CAROL W. BURTON, ESQ. |
| 1200 17TH STREET, SUITE 1500 |
| ONE TABOR CENTER |
| DENVER, CO 80202 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 39 CHEMIN DU CHAMP-DE-FILLES |
| 1228 PALN-LES-QUATES |
| GENEVA, SWITZERLAND |
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| SADLER, BREEN, MORASCH & COLBY, PS |
| 422 W. RIVERSIDE AVE,. SUITE 424 |
| SPOKANE, WA 99201 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1209 ORANGE STREET |
| WILMINGTON, DELAWARE 19801 |
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| SADLER BREEN MORASCH, ET AL. |
| 422 W. RIVERSIDE AVE. |
| SUITE 424 |
| SPOKANE, WA 99201 |
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Assignment:
4
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MERGER (SEE DOCUMENT FOR DETAILS).
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| 2215-B RENAISSANCE DRIVE |
| SUITE 5 |
| LAS VEGAS, NEVADA 89119 |
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| FOLEY & LARDNER |
| 150 EAST GILMAN STREET |
| VEREX PLAZA |
| MADISON, WI 53703 |
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