Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
Total Assignments:
1
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10810235
|
Filing Dt:
|
03/26/2004
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Inventors:
|
James N. Dieffenderfer, Richard W. Doing, Brian M. Stempel, Steven R. Testa et al
|
Title:
|
APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN AN INSTRUCTION CACHE AND A PIPELINE PROCESSOR
|
|
Assignment:
1
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
NEW ORCHARD ROAD |
ARMONK, NEW YORK 10504 |
|
|
|
IBM CORP. |
JOSCELYN G. COCKBURN |
3039 CORNWALLIS ROAD |
IP LAW DEPT. 9CCA/B002 |
RESEARCH TRIANGLE PARK, NC 27709 |
|
|
Search Results as of:
06/01/2024 01:22 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|