Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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09/30/2008
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Application #:
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11027292
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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08/11/2005
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Inventor:
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Hitanshu Dewan
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Title:
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AN IMPROVED SYSTEM FOR DELAY REDUCTION DURING TECHNOLOGY MAPPING IN FPGA
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| PLOT NO. 2 & 3, SECTOR 16A |
| INSTITUTIONAL AREA, NOIDA - 201 3001 |
| UTTAR PRADESH, INDIA |
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| PAUL F. RUSYN |
| GRAYBEAL JACKSON HALEY LLP |
| 155 - 108TH AVENUE N.E. |
| SUITE 350 |
| BELLEVUE, WA 98004-5973 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 39 CHEMIN DU CHAMP-DE-FILLES |
| 1228 PALN-LES-QUATES |
| GENEVA, SWITZERLAND |
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| SADLER, BREEN, MORASCH & COLBY, PS |
| 422 W. RIVERSIDE AVE,. SUITE 424 |
| SPOKANE, WA 99201 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1209 ORANGE STREET |
| WILMINGTON, DELAWARE 19801 |
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| SADLER BREEN MORASCH, ET AL. |
| 422 W. RIVERSIDE AVE. |
| SUITE 424 |
| SPOKANE, WA 99201 |
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Assignment:
4
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MERGER (SEE DOCUMENT FOR DETAILS).
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| 2215-B RENAISSANCE DRIVE |
| SUITE 5 |
| LAS VEGAS, NEVADA 89119 |
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| FOLEY & LARDNER |
| 150 EAST GILMAN STREET |
| VEREX PLAZA |
| MADISON, WI 53703 |
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