Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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11621915
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Filing Dt:
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01/10/2007
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Inventors:
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Oleg Levitsky, Chien-Chu Kuo, Dinesh Gupta
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Title:
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SYSTEM AND METHOD OF GENERATING HIERARCHICAL BLOCK-LEVEL TIMING CONSTRAINTS FROM CHIP-LEVEL TIMING CONSTRAINTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 95134 |
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| GEORGE L. FOUNTAIN |
| 3 HUTTON CENTRE |
| SUITE 850 |
| SANTA ANA, CA, CA 92707 |
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