Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12897777
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Filing Dt:
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10/04/2010
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Inventors:
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Dinesh Gupta, Oleg Levitsky
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Title:
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MULTI-PHASE MODELS FOR TIMING CLOSURE OF INTEGRATED CIRCUIT DESIGNS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2655 SEELY AVENUE |
SAN JOSE, CALIFORNIA 95134 |
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CADENCE DESIGN SYSTEMS C/O ALFORD LAW GR |
23052H ALICIA PARKWAY |
SUITE 201 |
MISSION VIEJO, CA 92692 |
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