Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10750584
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Filing Dt:
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12/31/2003
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Publication #:
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Pub Dt:
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06/30/2005
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Inventor:
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Edward A. Burton
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Title:
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DOWNLOCKING AND/OR UPGRADING INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2200 MISSION COLLEGE BLVD. |
| SANTA CLARA, CALIFORNIA 95052 |
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| SCHWABE, WILLIAMSON & WYATT, P.C. |
| ALOYSIUS T.C. AUYEUNG |
| SUITES 1600-1900 |
| 1211 SW FIFTH AVE. |
| PORTLAND, OR 97204 |
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