Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/07/2012
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Application #:
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12346956
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Filing Dt:
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12/31/2008
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Publication #:
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Pub Dt:
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07/01/2010
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Inventors:
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Maulik Joshi, Ivan Herrera Mejia, Joshua D. Louie
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Title:
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SIMULATING LOSS OF LOGIC POWER STATE DUE TO PROCESSOR POWER CONSERVATION STATE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2200 MISSION COLLEGE BLVD. |
| SANTA CLARA, CALIFORNIA 95052 |
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| RYDER IP LAW |
| C/O CPA GLOBAL |
| PO BOX 52050 |
| MINNEAPOLIS, MN 55402 |
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