Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13290250
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Filing Dt:
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11/07/2011
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Publication #:
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Pub Dt:
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05/09/2013
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Inventors:
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Prudhvi N. Nooney, Jaya Prakash Subramaniam Ganasan, Joseph L. Van Swearingen et al
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Title:
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LOW LATENCY CLOCK GATING SCHEME FOR POWER REDUCTION IN BUS INTERCONNECTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 5775 MOREHOUSE DRIVE |
| PATENT DEPARTMENT |
| SAN DIEGO, CALIFORNIA 92121-1714 |
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| QUALCOMM INCORPORATED |
| 5775 MOREHOUSE DRIVE |
| PATENT DEPARTMENT |
| SAN DIEGO, CA 92121-1714 |
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