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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
NONE
Issue Dt:
Application #:
13649584
Filing Dt:
10/11/2012
Publication #:
20140103985
Pub Dt:
04/17/2014
Inventors:
Alexander Andreev, Sergey Gribok, Marian Serban, Massimo Verita, Kee-Wei Sim, Kok-Hin Lew
Title:
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
Assignment: 1
Reel/Frame:
029714/0948Recorded: 01/29/2013Pages: 10
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
ANDREEV, ALEXANDER
Exec Dt:
01/14/2013
GRIBOK, SERGEY
Exec Dt:
11/01/2012
SERBAN, MARIAN
Exec Dt:
01/28/2013
VERITA, MASSIMO
Exec Dt:
01/29/2013
SIM, KEE-WEI
Exec Dt:
10/31/2012
LEW, KOK-HIN
Exec Dt:
10/31/2012
Assignee:
EASIC CORPORATION
2585 AUGUSTINE DRIVE, SUITE 100
SANTA CLARA, CALIFORNIA 95054
Correspondent:
SUITER SWANTZ PC LLO
14301 FNB PARKWAY
SUITE 220
OMAHA, NE 68154
Assignment: 2
Reel/Frame:
048559/0162Recorded: 03/11/2019Pages: 20
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
EASIC CORPORATION
Exec Dt:
03/01/2019
Assignee:
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondent:
ANGELA MILLER
C/O CPA GLOBAL
900 SECOND AVENUE SOUTH, SUITE 600
MINNEAPOLIS, MN 55402

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