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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
15556652
Filing Dt:
09/08/2017
Publication #:
20180052204
Pub Dt:
02/22/2018
Inventors:
HUAIYU ZHU, TAO YE, BING ZHOU, QUNXING JIANG, XIAOKAI WANG, SHENGJIAN SI, YUSEN PEI, TENG SHI
Title:
FPGA Clock Signal Self-detection Method
Assignment: 1
Reel/Frame:
043529/0095Recorded: 09/08/2017Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
JIANG, QUNXING
Exec Dt:
07/25/2017
WANG, XIAOKAI
Exec Dt:
07/25/2017
SI, SHENGJIAN
Exec Dt:
07/25/2017
PEI, YUSEN
Exec Dt:
07/25/2017
ZHU, HUAIYU
Exec Dt:
07/25/2017
YE, TAO
Exec Dt:
07/25/2017
ZHOU, BING
Exec Dt:
07/25/2017
SHI, TENG
Exec Dt:
07/25/2017
Assignee:
STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING CO., LTD.
NO. 428, EAST JIANGCHUAN ROAD, MINHANG DISTRICT
SHANGHAI, CHINA 200241
Correspondent:
KILE PARK REED & HOUTTEMAN LLC
3057 NUTLEY STREET
SUITE 819
FAIRFAX, VA 22031

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