Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/15/2022
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Application #:
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17183181
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Filing Dt:
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02/23/2021
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Publication #:
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Pub Dt:
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07/01/2021
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Inventors:
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Yuan-Sheng Fang, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Sasikanth Manipatruni et al
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Title:
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METHOD FOR USING AND FORMING LOW POWER FERROELECTRIC BASED MAJORITY LOGIC GATE ADDER
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 180 STEUART STREET #192524 |
| SAN FRANCISCO, CALIFORNIA 94105 |
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| GREEN, HOWARD, & MUGHAL LLP |
| 5 CENTERPOINTE DR. |
| SUITE 400 |
| LAKE OSWEGO, OR 97035 |
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