Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/11/2023
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Application #:
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17861412
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Filing Dt:
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07/11/2022
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Publication #:
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Pub Dt:
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12/22/2022
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Inventors:
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Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
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Title:
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Silicon-Containing Layer for Bit Line Resistance Reduction
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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3050 BOWERS AVENUE |
SANTA CLARA, CALIFORNIA 95054 |
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SERVILLA WHITNEY LLC |
33 WOOD AVENUE SOUTH |
SUITE 830 |
ISELIN, NJ 08830 |
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05/31/2024 11:43 PM
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