Total properties:
103
Page
1
of
2
Pages:
1 2
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09057598
|
Filing Dt:
|
04/08/1998
|
|
Title:
|
METHOD OF FABRICATING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09057599
|
Filing Dt:
|
04/08/1998
|
|
Title:
|
METHOD FOR MANUFACTURING CHARGE STORAGE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
09057925
|
Filing Dt:
|
04/08/1998
|
|
Title:
|
METHOD FOR MANUFACTURING CHARGE STORAGE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09063021
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
METHOD OF FORMING BURIED DIFFUSION JUNCTIONS IN CONJUNCTION WITH SHALLOW-TRENCH ISOLATION STRUCTURES IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09063022
|
Filing Dt:
|
04/20/1998
|
|
Title:
|
PROCESS OF FABRICATING BURIED DIFFUSION JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09073920
|
Filing Dt:
|
05/06/1998
|
|
Title:
|
METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE USING A HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09075297
|
Filing Dt:
|
05/08/1998
|
|
Title:
|
ETCHING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09076243
|
Filing Dt:
|
05/11/1998
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
|
Title:
|
METHOD OF FABRICATING AN OPENING WITH DEEP ULTRA-VIOLET PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09076362
|
Filing Dt:
|
05/11/1998
|
|
Title:
|
SILICON-ON-INSULATOR MOS STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09076363
|
Filing Dt:
|
05/11/1998
|
|
Title:
|
BURIED CHANNEL VERTICAL DOUBLE DIFFUSION MOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09076364
|
Filing Dt:
|
05/11/1998
|
|
Title:
|
APPARATUS FOR PERFORMING CHEMICAL VAPOR DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09082388
|
Filing Dt:
|
05/20/1998
|
|
Title:
|
SELF-ALIGNED METAL NITRIDE FOR COPPER PASSIVATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09082657
|
Filing Dt:
|
05/21/1998
|
|
Title:
|
METHOD FOR FORMING A BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09082658
|
Filing Dt:
|
05/21/1998
|
|
Title:
|
TRENCH CONTACT STRUCTURE OF SILICON ON INSULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09082659
|
Filing Dt:
|
05/21/1998
|
|
Title:
|
METHOD FOR RECYCLING MONITORING CONTROL WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09089248
|
Filing Dt:
|
06/02/1998
|
|
Title:
|
METHOD OF FABRICATING A CYLINDRICAL CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09103384
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
METHOD OF FABRICATING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09107159
|
Filing Dt:
|
06/09/1998
|
|
Title:
|
STRUCTURE OF A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09112951
|
Filing Dt:
|
07/09/1998
|
|
Title:
|
METHOD OF REMOVING COPPER OXIDE WITHIN VIA HOLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09121154
|
Filing Dt:
|
07/22/1998
|
|
Title:
|
FABRICATING METHOD OF A METAL GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09122618
|
Filing Dt:
|
07/22/1998
|
|
Title:
|
FABRICATION METHOD FOR A FIELD EMISSION DISPLAY EMITTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09127998
|
Filing Dt:
|
07/31/1998
|
|
Title:
|
METHOD OF MANUFACTURING A DUAL CYLINDER-SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09136553
|
Filing Dt:
|
08/19/1998
|
|
Title:
|
METHOD OF FABRICATING IMPLANTATION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09145711
|
Filing Dt:
|
09/02/1998
|
|
Title:
|
METHOD OF FABRICATING DRAM CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09150948
|
Filing Dt:
|
09/10/1998
|
|
Title:
|
METHOD AND APPARATUS OF UNINTERRUPTED SLURRY SUPPLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09174388
|
Filing Dt:
|
10/14/1998
|
|
Title:
|
METHOD OF MANUFACTURING CYLINDRICAL SHAPED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09178150
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
METHOD OF MANUFACTURING DRAM CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09186530
|
Filing Dt:
|
11/05/1998
|
|
Title:
|
METHOD OF DETERMINING A TIME TO CLEAN A LOW PRESSURE CHEMICAL VAPOR DEPOSITION (LPCVD) SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
09186544
|
Filing Dt:
|
11/05/1998
|
|
Title:
|
METHOD OF MANUFACTURING A SHALLOW TRENCH ISOLATION ALIGNMENT MARK
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09187062
|
Filing Dt:
|
11/05/1998
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
|
Title:
|
METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING A DUMMY PATTERN IN THE WIDER TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09187112
|
Filing Dt:
|
11/05/1998
|
|
Title:
|
METHOD FOR FORMING AN INSULATING FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09191677
|
Filing Dt:
|
11/13/1998
|
|
Title:
|
METHOD OF MANUFACTURING EMBEDDED DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09205912
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD OF FABRICATING A DUAL DAMASCENE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09206052
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD OF FORMING INTERCONNECTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09206177
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD OF INSPECTING WAFER WATER MARK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09206187
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD FOR PREVENTING DOPANT DIFFUSION IN DUAL GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09215586
|
Filing Dt:
|
12/17/1998
|
|
Title:
|
METHOD FOR CLEANING A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09227626
|
Filing Dt:
|
01/08/1999
|
|
Title:
|
METHOD OF FABRICATING BARRIER LAYER IN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09227698
|
Filing Dt:
|
01/08/1999
|
|
Title:
|
METHOD OF RECONSTRUCTING ALIGNMENT MARK DURING STI PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09235262
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
METHOD FORMING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09237207
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
METHOD TO CROWN CAPACITOR FOR HIGH DENSITY DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09237495
|
Filing Dt:
|
01/25/1999
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
|
Title:
|
METHOD FOR RESTORING AN ALIGNMENT MARK AFTER PLANARIZATION OF A DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09237496
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
METHOD FOR FABRICATING AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09237595
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
METHOD FOR FABRICATING A GATE ELETRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09241739
|
Filing Dt:
|
02/01/1999
|
|
Title:
|
METHOD FOR FORMING SHALLOW TRENCH ISOLATION REGION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09250619
|
Filing Dt:
|
02/16/1999
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
|
Title:
|
METHOD OF FORMING AN OPENING IN A DIELECTRIC LAYER IN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09250620
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
METHOD OF FABRICATING DIELECTRIC LAYER IN ALIGNMENT MARKER AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09266660
|
Filing Dt:
|
03/11/1999
|
|
Title:
|
VIBRATION DAMPER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09270030
|
Filing Dt:
|
03/16/1999
|
|
Title:
|
METHOD OF MANUFACTURING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09280357
|
Filing Dt:
|
03/29/1999
|
|
Title:
|
METHOD FOR MANUFACTURING A MOS DEVICE WITH MULTIPLE THRESHOLD VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09280761
|
Filing Dt:
|
03/29/1999
|
|
Title:
|
METHOD OF FABRICATING SUB-QUARTER-MICRON SALICIDE POLYSILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09282016
|
Filing Dt:
|
03/29/1999
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
|
Title:
|
WAFERLESS SEASONING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09282019
|
Filing Dt:
|
03/29/1999
|
|
Title:
|
METHOD OF FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09286008
|
Filing Dt:
|
04/05/1999
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2001
| | | | |
|
Title:
|
METHOD FOR CLEANING INTERIOR OF ETCHING CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09286357
|
Filing Dt:
|
04/05/1999
|
|
Title:
|
METHOD OF FABRICATING SELF-ALIGNED NODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09293421
|
Filing Dt:
|
04/16/1999
|
|
Title:
|
METHOD OF FABRICATING FIELD EFFECT TRANSISTOR WITH SILICIDE SIDEWALL SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09293437
|
Filing Dt:
|
04/16/1999
|
|
Title:
|
METHOD OF FABRICATIG SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09306253
|
Filing Dt:
|
05/06/1999
|
|
Title:
|
METHOD OF FABRICATING DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09315799
|
Filing Dt:
|
05/21/1999
|
|
Title:
|
METHOD OF FABRICATING A SEMICONDUCTIVE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09322058
|
Filing Dt:
|
05/27/1999
|
|
Title:
|
METHOD FOR MANUFACTURING DYNAMIC RANDOM ACCESS MEMORY CAPABLE OF INCREASING THE STORAGE CAPACITY OF THE CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09328057
|
Filing Dt:
|
06/08/1999
|
|
Title:
|
POSITION DETECTOR FOR A SPIN-DRYING MACHINE USED IN INTEGRATED CIRCUIT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09328863
|
Filing Dt:
|
06/09/1999
|
|
Title:
|
METHOD OF MEASURING MISALIGNMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09330432
|
Filing Dt:
|
06/08/1999
|
|
Title:
|
METHOD OF DEFINING A CONDUCTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09340929
|
Filing Dt:
|
06/28/1999
|
|
Title:
|
FABRICATION METHOD FOR GATE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09348371
|
Filing Dt:
|
07/07/1999
|
|
Title:
|
METHOD FOR FORMING GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09348395
|
Filing Dt:
|
07/07/1999
|
|
Title:
|
METHOD OF FABRICATING A MOS DEVICE USING A SACRIFICIAL LAYER AND SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09348408
|
Filing Dt:
|
07/07/1999
|
|
Publication #:
|
|
Pub Dt:
|
06/14/2001
| | | | |
|
Title:
|
METHOD OF MANUFACTURING BOTTOM ELECTRODE OF CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09348884
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
METHOD OF FABRICATING SHALLOW TRENCH ISOLATION (STI)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09356962
|
Filing Dt:
|
07/19/1999
|
|
Title:
|
METHOD OF IN-LINE TEMPERATURE MONITORING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09358339
|
Filing Dt:
|
07/21/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH FAST WRITE RECOVERY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09359518
|
Filing Dt:
|
07/23/1999
|
|
Title:
|
FABRICATION METHOD FOR AN INSULATION STRUCTURE HAVING A LOW DIELECTRIC CONSTANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09371472
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD OF MANUFACTURING INTER-METAL DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09372430
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD FOR FORMING MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09372432
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD OF FABRICATING TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09372433
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD OF FABRICATING COPPER DAMASCENE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09375619
|
Filing Dt:
|
08/17/1999
|
|
Title:
|
SALICIDE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09375672
|
Filing Dt:
|
08/17/1999
|
|
Title:
|
METHOD OF MANUFACTURING AN INDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09375688
|
Filing Dt:
|
08/17/1999
|
|
Title:
|
SEMICONDUCTOR INDUCTOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09383031
|
Filing Dt:
|
08/25/1999
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2001
| | | | |
|
Title:
|
METHOD FOR CONTROLLING CRITICAL DIMENSION OF CONTACT OPENING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
09385737
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
SENSE/OUTPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09389817
|
Filing Dt:
|
09/03/1999
|
|
Title:
|
METHOD OF ELIMINATING SIGNAL SKEW IN A SYNCHRONIZED DYNAMIC RANDOM-ACCESS MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09389999
|
Filing Dt:
|
09/03/1999
|
|
Title:
|
METHOD OF FABRICATING CAPACITOR DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09390104
|
Filing Dt:
|
09/03/1999
|
|
Title:
|
METHOD OF FABRICATING NODE CONTACT OPENING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09392268
|
Filing Dt:
|
09/09/1999
|
|
Title:
|
DAMASCENE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09392879
|
Filing Dt:
|
09/09/1999
|
|
Title:
|
VOLTAGE REGULATOR CAPABLE OF IMPROVING SYSTEM RESPONSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09393049
|
Filing Dt:
|
09/09/1999
|
|
Title:
|
METHOD FOR FORMING AN INTER-LAYER DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09395906
|
Filing Dt:
|
09/11/1999
|
|
Title:
|
METHOD FOR MANUFACTURING DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09396995
|
Filing Dt:
|
09/15/1999
|
|
Title:
|
OPTICAL METHOD OF MEASURING TRENCH DEPTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09406505
|
Filing Dt:
|
09/28/1999
|
|
Title:
|
METHOD OF FABRICATING LOWER ELECTRODE OF CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09414986
|
Filing Dt:
|
10/07/1999
|
|
Title:
|
MULTI-CHIP SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09417508
|
Filing Dt:
|
10/14/1999
|
|
Title:
|
METHOD AND TESTING SYSTEM FOR MEASURING CONTACT RESISTANCE FOR PIN OF INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09418144
|
Filing Dt:
|
10/14/1999
|
|
Title:
|
METHOD FOR AVOIDING PLASMA DAMAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09420049
|
Filing Dt:
|
10/18/1999
|
|
Title:
|
METHOD OF FABRICATING STI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09421308
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
FABRICATION METHOD FOR A VERTICAL MOS TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09421309
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
METHOD FOR FORMING DIFFERENT PATTERNS USING ONE MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09428372
|
Filing Dt:
|
10/28/1999
|
|
Title:
|
METHOD FOR FORMING OPENING IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09428735
|
Filing Dt:
|
10/28/1999
|
|
Title:
|
METHOD OF FABRICATING A SILICIDE LANDING PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09430706
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
METHOD OF FABRICATING A DYNAMIC RANDOM-ACCESS MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09434047
|
Filing Dt:
|
11/04/1999
|
|
Title:
|
METHOD OF INCREASING GATE SURFACE AREA FOR DEPOSITING SILICIDE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09434688
|
Filing Dt:
|
11/05/1999
|
|
Title:
|
METHOD OF FABRICATING A LOWER ELECTRODE OF CAPACITOR
|
|
