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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:010848/0087   Pages: 12
Recorded: 06/19/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 56
1
Patent #:
5649162
Issue Dt:
07/15/1997
Application #:
08066400
Filing Dt:
05/24/1993
Title:
LOCAL BUS INTERFACE
2
Patent #:
5666522
Issue Dt:
09/09/1997
Application #:
08189254
Filing Dt:
01/28/1994
Title:
VARIABLE SPEED CONTROLLER
3
Patent #:
5581793
Issue Dt:
12/03/1996
Application #:
08353160
Filing Dt:
12/09/1994
Title:
A SYSTEM FOR BYPASSING SETUP STATES IN A BUS OPERATION
4
Patent #:
5664140
Issue Dt:
09/02/1997
Application #:
08444750
Filing Dt:
05/19/1995
Title:
PROCESSOR TO MEMORY INTERFACE LOGIC FOR USE IN A COMPUTER SYSTEM USING A MULTIPLEXED MEMORY ADDRESS
5
Patent #:
5692165
Issue Dt:
11/25/1997
Application #:
08526988
Filing Dt:
09/12/1995
Title:
MEMORY CONTROLLER WITH LOW SKEW CONTROL SIGNAL
6
Patent #:
6006310
Issue Dt:
12/21/1999
Application #:
08531134
Filing Dt:
09/20/1995
Title:
A SINGLE MEMORY DEVICE THAT FUNCTIONS AS A MULTI-WAY SET ASSICIATE CACHE MEMORY
7
Patent #:
5905910
Issue Dt:
05/18/1999
Application #:
08657601
Filing Dt:
05/31/1996
Title:
SYSTEM FOR MULTI-THREADED DISK DRIVE OPERATION IN A COMPUTER SYSTEM USING AN INTERRUPT PROCESSOR SOFTWARE MODULE ANALYZING AND PROCESSING INTERRUPT SIGNALS TO CONTROL DATA TRANSFER
8
Patent #:
5867733
Issue Dt:
02/02/1999
Application #:
08657968
Filing Dt:
06/04/1996
Title:
MASS DATA STORAGE CONTROLLER PERMITTING DATA TO BE DIRECTLY TRANSFERRED BETWEEN STORAGE DEVICES WITHOUT TRANSFERRING DATA TO MAIN MEMORY AND WITHOUT TRANSFERRING DATA OVER INPUT-OUTPUT BUS
9
Patent #:
5813029
Issue Dt:
09/22/1998
Application #:
08677267
Filing Dt:
07/09/1996
Title:
UPGRADEABLE CACHE CIRCUIT USING HIGH SPEED MULTIPLEXER
10
Patent #:
5805835
Issue Dt:
09/08/1998
Application #:
08679834
Filing Dt:
07/15/1996
Title:
PARALLEL ARCHITECTURE COMPUTER SYSTEM AND METHOD
11
Patent #:
5822549
Issue Dt:
10/13/1998
Application #:
08680157
Filing Dt:
07/15/1996
Title:
COMPUTER SYSTEM AND BUS CONTROLLER FOR CONTROLLING ACCESS TO A COMPUTER BUS
12
Patent #:
5815674
Issue Dt:
09/29/1998
Application #:
08680443
Filing Dt:
07/15/1996
Title:
METHOD AND SYSTEM FOR INTERFACING A PLURALITY OF BUS REQUESTERS WITH A COMPUTER BUS
13
Patent #:
5771358
Issue Dt:
06/23/1998
Application #:
08680446
Filing Dt:
07/15/1996
Title:
METHOD AND SYSTEM FOR APPORTIONING COMPUTER BUS BANDWIDTH
14
Patent #:
5740380
Issue Dt:
04/14/1998
Application #:
08680464
Filing Dt:
07/15/1996
Title:
METHOD AND SYSTEM FOR APPORTIONING COMPUTER BUS BANDWIDTH
15
Patent #:
5745772
Issue Dt:
04/28/1998
Application #:
08693510
Filing Dt:
08/02/1996
Title:
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER
16
Patent #:
5857084
Issue Dt:
01/05/1999
Application #:
08725019
Filing Dt:
10/02/1996
Title:
HIERARCHICAL BUS STRUCTURE ACCESS SYSTEM
17
Patent #:
5878235
Issue Dt:
03/02/1999
Application #:
08725576
Filing Dt:
10/03/1996
Title:
METHOD AND SYSTEM FOR CONCURRENT COMPUTER TRANSACTION PROCESSING
18
Patent #:
5862314
Issue Dt:
01/19/1999
Application #:
08741603
Filing Dt:
11/01/1996
Title:
SYSTEM AND METHOD FOR REMAPPING DEFECTIVE MEMORY LOCATIONS
19
Patent #:
5905858
Issue Dt:
05/18/1999
Application #:
08742773
Filing Dt:
11/01/1996
Title:
SYSTEM AND METHOD FOR MEMORY ERROR HANDLING
20
Patent #:
5933852
Issue Dt:
08/03/1999
Application #:
08744958
Filing Dt:
11/07/1996
Title:
SYSTEM AND METHOD FOR ACCELERATED REMAPPING OF DEFECTIVE MEMORY LOCATIONS
21
Patent #:
5805841
Issue Dt:
09/08/1998
Application #:
08758059
Filing Dt:
11/27/1996
Title:
SYMMETRIC PARALLEL MULTI-PROCESSING BUS ARCHITECTURE
22
Patent #:
5911077
Issue Dt:
06/08/1999
Application #:
08769424
Filing Dt:
12/19/1996
Title:
SYSTEM FOR MULTITHREADED DISK DRIVE OPERATION IN A COMPUTER SYSTEM
23
Patent #:
5887157
Issue Dt:
03/23/1999
Application #:
08810401
Filing Dt:
03/04/1997
Title:
LOCAL BUS INTERFACE
24
Patent #:
5950229
Issue Dt:
09/07/1999
Application #:
08815817
Filing Dt:
03/12/1997
Title:
SYSTEM FOR ACCELERATING MEMORY BANDWIDTH
25
Patent #:
5926838
Issue Dt:
07/20/1999
Application #:
08820595
Filing Dt:
03/19/1997
Title:
INTERFACE FOR HIGH SPEED MEMORY
26
Patent #:
5933859
Issue Dt:
08/03/1999
Application #:
08846105
Filing Dt:
04/25/1997
Title:
PROCESSOR TO MEMORY INTERFACE LOGIC FOR USE IN A COMPUTER SYSTEM USING A MULTIPLEXED MEMORY ADDRESS
27
Patent #:
5920881
Issue Dt:
07/06/1999
Application #:
08859015
Filing Dt:
05/20/1997
Title:
METHOD AND SYSTEM FOR USING A VIRTUAL REGISTER FILE IN SYSTEM MEMORY
28
Patent #:
5935233
Issue Dt:
08/10/1999
Application #:
08859894
Filing Dt:
05/21/1997
Title:
COMPUTER SYSTEM WITH A SWITCH INTERCONNECTOR FOR COMPUTER DEVICES
29
Patent #:
5974239
Issue Dt:
10/26/1999
Application #:
08873213
Filing Dt:
06/11/1997
Title:
DATA TRANSFER METHOD FOR A BUS DEVICE IN A COMPUTER SYSTEM BY PLACING FIRST AND SECOND ADDRESSES CORRESPONDING TO A BRIDGE AND WITH THE BUS DEVICE RESPECTIVELY ON A BUS
30
Patent #:
5832418
Issue Dt:
11/03/1998
Application #:
08881716
Filing Dt:
06/23/1997
Title:
APPARATUS FOR TESTING A CONTROLLER WITH RANDOM CONTRAINTS
31
Patent #:
5857095
Issue Dt:
01/05/1999
Application #:
08881918
Filing Dt:
06/25/1997
Title:
METHOD FOR ALIGNING A CONTROL SIGNAL AND A CLOCK SIGNAL
32
Patent #:
5819076
Issue Dt:
10/06/1998
Application #:
08882559
Filing Dt:
06/25/1997
Title:
MEMORY CONTROLLER WITH LOW SKEW CONTROL SIGNAL
33
Patent #:
6018792
Issue Dt:
01/25/2000
Application #:
08886908
Filing Dt:
07/02/1997
Title:
APPARATUS FOR PERFORMING A LOW LATENCY MEMORY READ WITH CONCURRENT SNOOP
34
Patent #:
5991855
Issue Dt:
11/23/1999
Application #:
08887039
Filing Dt:
07/02/1997
Title:
LOW LATENCY MEMORY READ WITH CONCURRENT PIPELINED SNOOPS
35
Patent #:
5909701
Issue Dt:
06/01/1999
Application #:
08896668
Filing Dt:
07/18/1997
Title:
INTERFACE FOR HIGH SPEED MEMORY
36
Patent #:
5898891
Issue Dt:
04/27/1999
Application #:
08896744
Filing Dt:
07/18/1997
Title:
METHOD FOR TRANSFERRING DATA DIRECTLY BETWEEN THE FIRST AND SECOND DATA STORAGE DEVICES WITHOUT TRANSFERRING DATA TO THE MEMORY ARRAY OR OVER THE INPUT-OUTPUT BUS
37
Patent #:
5911078
Issue Dt:
06/08/1999
Application #:
08905889
Filing Dt:
07/31/1997
Title:
METHOD FOR MULTITHREADED DISK DRIVE OPERATION IN A COMPUTER SYSTEM
38
Patent #:
6000001
Issue Dt:
12/07/1999
Application #:
08924755
Filing Dt:
09/05/1997
Title:
MULTIPLE PRIORITY ACCELERATED GRAPHICS PORT (AGP) REQUEST QUEUE
39
Patent #:
5903776
Issue Dt:
05/11/1999
Application #:
08924756
Filing Dt:
09/05/1997
Title:
MULTIPLE PRIORITY ACCELERATED GRAPHICS PORT (AGP) REQUEST QUEUE
40
Patent #:
6026463
Issue Dt:
02/15/2000
Application #:
08927233
Filing Dt:
09/10/1997
Title:
METHOD FOR IMPROVING DATA TRANSFER RATES FOR USER DATA STORED ON A DISK STORAGE DEVICE
41
Patent #:
5953743
Issue Dt:
09/14/1999
Application #:
08928557
Filing Dt:
09/12/1997
Title:
METHOD FOR ACCELERATING MEMORY BANDWIDTH
42
Patent #:
6018807
Issue Dt:
01/25/2000
Application #:
08937860
Filing Dt:
09/25/1997
Title:
SIMULATION "BUS CONTENTION" DETECTION
43
Patent #:
5931937
Issue Dt:
08/03/1999
Application #:
08948802
Filing Dt:
10/10/1997
Title:
SYMMETRIC PARALLEL MULTI-PROCESSING BUS ARCHITECTURE
44
Patent #:
5968139
Issue Dt:
10/19/1999
Application #:
08960713
Filing Dt:
10/30/1997
Title:
SYSTEM AND METHOD FOR IDENTIFICATION OF COMPPUTER DATA STORAGE DEVICES
45
Patent #:
6029253
Issue Dt:
02/22/2000
Application #:
08960776
Filing Dt:
10/30/1997
Title:
METHOD FOR SYNCHRONIZING DATA WITH A BI-DIRECTIONAL BUFFER
46
Patent #:
5829036
Issue Dt:
10/27/1998
Application #:
08961698
Filing Dt:
10/31/1997
Title:
METHOD FOR PROVIDING AND OPERATING UPGRADEABLE CACHE CIRCUITRY
47
Patent #:
5905878
Issue Dt:
05/18/1999
Application #:
08970909
Filing Dt:
11/14/1997
Title:
METHOD FOR CONTROLLING ACCESS TO A COMPUTER BUS
48
Patent #:
5889726
Issue Dt:
03/30/1999
Application #:
08971743
Filing Dt:
11/17/1997
Title:
APPARATUS FOR PROVIDING ADDITIONAL LATENCY FOR SYNCHRONOUSLY ACCESSED MEMORY
49
Patent #:
5919252
Issue Dt:
07/06/1999
Application #:
08977640
Filing Dt:
11/24/1997
Title:
PROCESS AND APPARATUS FOR ADAPTIVE BUS TERMINATION
50
Patent #:
6037803
Issue Dt:
03/14/2000
Application #:
08990060
Filing Dt:
12/12/1997
Title:
INTEGRATED CIRCUIT HAVING TWO MODES OF I/O PAD TERMINATION
51
Patent #:
5978872
Issue Dt:
11/02/1999
Application #:
09066526
Filing Dt:
04/24/1998
Title:
METHOD AND SYSTEM FOR CONCURRENT COMPUTER TRANSACTION PROCESSING
52
Patent #:
6029223
Issue Dt:
02/22/2000
Application #:
09067338
Filing Dt:
04/27/1998
Title:
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER
53
Patent #:
6006166
Issue Dt:
12/21/1999
Application #:
09073378
Filing Dt:
05/05/1998
Title:
APPARATUS FOR TESTING A CONTROLLER WITH RANDOM CONSTRAINTS
54
Patent #:
6026046
Issue Dt:
02/15/2000
Application #:
09111244
Filing Dt:
07/07/1998
Title:
APPARATUS FOR DECODING ADDRESSES
55
Patent #:
5991843
Issue Dt:
11/23/1999
Application #:
09176059
Filing Dt:
10/20/1998
Title:
METHOD AND SYSTEM FOR CONCURRENT COMPUTER TRANSACTION PROCESSING
56
Patent #:
6031787
Issue Dt:
02/29/2000
Application #:
09200007
Filing Dt:
11/25/1998
Title:
APPARATUS FOR PROVIDING ADDITIONAL LATENCY FOR SYNCHRONOUSLY ACCESSED MEMORY
Assignor
1
MICRON ELECTRONICS, INC.
Exec Dt:
03/17/2000
Assignee
1
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY
BOISE, IDAHO 83716
Correspondence name and address
MICRON TECHNOLOGY, INC.
WALTER D. FIELDS
8000 S. FEDERAL WAY
BOISE, ID 83706-9632

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