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Total properties:
56
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Patent #:
|
|
Issue Dt:
|
05/04/1982
|
Application #:
|
06137764
|
Filing Dt:
|
04/07/1980
|
|
Title:
|
NON-VOLATILE EPROM WITH INCREASED EFFICIENCY
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Patent #:
|
|
Issue Dt:
|
11/30/1982
|
Application #:
|
06153251
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Filing Dt:
|
05/27/1980
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Title:
|
NON-VOLATILE EPROM WITH ENCHANCED DRAIN OVERLAP FOR INCREASED EFFICIENCY
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|
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Patent #:
|
|
Issue Dt:
|
10/18/1983
|
Application #:
|
06184739
|
Filing Dt:
|
09/08/1980
|
|
Title:
|
NON-VOLATILE EPROM AND EEPROM WITH INCREASED EFFICIENCY
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|
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|
Patent #:
|
|
Issue Dt:
|
03/10/1987
|
Application #:
|
06669198
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Filing Dt:
|
11/07/1984
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Title:
|
SINGLE LAYER POLYCRYSTALLINE FLOATING GATE
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Patent #:
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|
Issue Dt:
|
08/09/1988
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Application #:
|
06728738
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Filing Dt:
|
04/30/1985
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|
Title:
|
INPUT CIRCUIT FOR PROTECTING AGAINST DAMAGE CAUSED BY ELECTROSTATIC DISCHARGE
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Patent #:
|
|
Issue Dt:
|
07/19/1988
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Application #:
|
06902236
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Filing Dt:
|
08/29/1986
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Title:
|
NONVOLATILE FLOATING GATE TRANSISTOR STRUCTURE
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|
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Patent #:
|
|
Issue Dt:
|
05/07/1991
|
Application #:
|
07137782
|
Filing Dt:
|
12/24/1987
|
|
Title:
|
ON-CHIP HIGH VOLTAGE GENERATOR AND REGULATOR IN AN INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/1991
|
Application #:
|
07189874
|
Filing Dt:
|
05/03/1988
|
|
Title:
|
EEPROM WITH IMPROVED ERASE STRUCTURE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/23/1991
|
Application #:
|
07214562
|
Filing Dt:
|
07/01/1988
|
|
Title:
|
OPAQUE COVER FOR PREVENTING ERASURE OF AN EPROM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/1990
|
Application #:
|
07231122
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Filing Dt:
|
08/11/1988
|
|
Title:
|
DECODER FOR A MEMORY ADDRESS BUS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/1990
|
Application #:
|
07231123
|
Filing Dt:
|
08/11/1988
|
|
Title:
|
OUTPUT CIRCUIT FOR DRIVING A MEMORY DEVICE OUTPUT LEAD INCLUDING A THREE-STATE INVERTING BUFFER AND A TRANSFER GATE COUPLED BETWEEN THE BUFFER INPUT LEAD AND THE BUFFER OUTPUT LEAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/1991
|
Application #:
|
07258926
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Filing Dt:
|
10/17/1988
|
|
Title:
|
DECODER FOR A FLOATING GATE MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/1991
|
Application #:
|
07258952
|
Filing Dt:
|
10/17/1988
|
|
Title:
|
SPLIT GATE MEMORY ARRAY HAVING STAGGERED FLOATING GATE ROWS AND METHOD FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/1990
|
Application #:
|
07483285
|
Filing Dt:
|
02/20/1990
|
|
Title:
|
CIRCUIT FOR CONTROLLING A FLASH EEPROM HAVING THREE DISTINCT MODES OF OPERATION BY ALLOWING MULTIPLE FUNCTIONALITY OF A SINGLE PIN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/1991
|
Application #:
|
07516025
|
Filing Dt:
|
04/27/1990
|
|
Title:
|
ON-CHIP HIGH VOLTAGE GENERATOR AND REGULATOR IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1992
|
Application #:
|
07537553
|
Filing Dt:
|
06/13/1990
|
|
Title:
|
EPROM VIRTUAL GROUND ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1993
|
Application #:
|
07539657
|
Filing Dt:
|
06/13/1990
|
|
Title:
|
EPROM VIRTUAL GROUND ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/1994
|
Application #:
|
07609123
|
Filing Dt:
|
10/31/1990
|
|
Title:
|
PROGRAMMABLE CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
07690133
|
Filing Dt:
|
04/23/1991
|
|
Title:
|
SRAM WITH A PROGRAMMABLE REFERENCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/1994
|
Application #:
|
07752380
|
Filing Dt:
|
08/30/1991
|
|
Title:
|
PAGE REGISTER WITH A DON'T CARE FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1992
|
Application #:
|
07752733
|
Filing Dt:
|
08/30/1991
|
|
Title:
|
GLITCH FREE POWER-UP FOR A PROGRAMMABLE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/1994
|
Application #:
|
07846183
|
Filing Dt:
|
03/04/1992
|
|
Title:
|
EASILY MANUFACTURABLE COMPACT EPROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/1994
|
Application #:
|
07879407
|
Filing Dt:
|
05/06/1992
|
|
Title:
|
STRUCTURE AND METHOD FOR COMPENSATING FOR PROGRAMMING THRESHOLD SHIFT DUE TO NEIGHBOR EFFECT IN AN ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
07908595
|
Filing Dt:
|
06/30/1992
|
|
Title:
|
FAST EPROM ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/1995
|
Application #:
|
08046156
|
Filing Dt:
|
04/13/1993
|
|
Title:
|
CIRCUIT FOR PERFORMING ARITHMETIC OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/1995
|
Application #:
|
08091795
|
Filing Dt:
|
07/14/1993
|
|
Title:
|
PERIPHERAL PORT WITH VOLATILE AND NON-VOLATILE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/1995
|
Application #:
|
08170130
|
Filing Dt:
|
12/20/1993
|
|
Title:
|
ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1997
|
Application #:
|
08212165
|
Filing Dt:
|
03/11/1994
|
|
Title:
|
SCALABLE EPROM ARRAY WITH THICK AND THIN NON-FIELD OXIDE GATE INSULATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/1996
|
Application #:
|
08212176
|
Filing Dt:
|
03/11/1994
|
|
Title:
|
FLASH EEPROM AND EPROM ARRAYS WITH SELECT TRANSISTORS WITHIN THE BIT LINE PITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/1996
|
Application #:
|
08242929
|
Filing Dt:
|
05/16/1994
|
|
Title:
|
APPARATUS AND METHOD FOR PRODUCING AN OUTPUT SIGNAL FROM A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08242947
|
Filing Dt:
|
05/16/1994
|
|
Title:
|
UNIT FOR STABILIZING VOLTAGE ON A CAPACITIVE NODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/1996
|
Application #:
|
08245087
|
Filing Dt:
|
05/17/1994
|
|
Title:
|
SOURCE PRE-CHARGE SYSTEM IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/1995
|
Application #:
|
08291252
|
Filing Dt:
|
08/16/1994
|
|
Title:
|
MOS SRAM CELL WITH OPEN BASE BIPOLAR LOADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/1996
|
Application #:
|
08330211
|
Filing Dt:
|
10/21/1994
|
|
Title:
|
SENSE AMPLIFIER WITH READ CURRENT TRACKING AND ZERO STANDBY POWER CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1998
|
Application #:
|
08634282
|
Filing Dt:
|
04/18/1996
|
|
Title:
|
ROW DECODER HAVING TRIPLE TRANSISTOR WORD LINE DRIVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08639281
|
Filing Dt:
|
04/25/1996
|
|
Title:
|
LOW POWER PROGRAMMABLE RING OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08665136
|
Filing Dt:
|
06/13/1996
|
|
Title:
|
OPERATING METHOD FOR ROM ARRAY WHICH MINIMIZES BAND-TO-BAND TUNNELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/1997
|
Application #:
|
08665150
|
Filing Dt:
|
06/13/1996
|
|
Title:
|
MANUFACTURING METHOD FOR ROM ARRAY WITH MINIMAL BAND-TO-BAND TUNNELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08665151
|
Filing Dt:
|
06/13/1996
|
|
Title:
|
SELF ADJUSTING SENSE AMPLIFIER CLOCK DELAY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08665191
|
Filing Dt:
|
06/13/1996
|
|
Title:
|
FIRST READ CYCLE CIRCUIT FOR SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08742710
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
MICROCONTROLLER ACCESSIBLE MACROCELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08749615
|
Filing Dt:
|
11/18/1996
|
|
Title:
|
UNIT FOR MAINTAINING INFORMATION REGARDING THE STATE OF A DEVICE DURING BATTERY POWER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08749616
|
Filing Dt:
|
11/18/1996
|
|
Title:
|
BACKUP BATTERY SWITCH WITH FIRST POWER UP CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08749617
|
Filing Dt:
|
11/18/1996
|
|
Title:
|
BATTERY BACKED CONFIGURABLE OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08749618
|
Filing Dt:
|
11/18/1996
|
|
Title:
|
BACKUP BATTERY SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/1999
|
Application #:
|
08806559
|
Filing Dt:
|
02/25/1997
|
|
Title:
|
SCALABLE EPROM ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08806560
|
Filing Dt:
|
02/25/1997
|
|
Title:
|
A CHARGE PUMP CIRCUIT FOR VOLTAGE BOOSTING IN INTEGRATED SEMICONDUCTOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08847739
|
Filing Dt:
|
04/22/1997
|
|
Title:
|
PROGRAMMABLE LOGIC DEVICE PRODUCING A COMPLEMENTARY BIT LINE SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08936849
|
Filing Dt:
|
09/24/1997
|
|
Title:
|
DUAL BIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08953690
|
Filing Dt:
|
10/17/1997
|
|
Title:
|
PROGRAMMABLE SENSE AMPLIFIER DELAY (PSAD) CIRCUIT WHICH IS MATCHED TO THE MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08953714
|
Filing Dt:
|
10/17/1997
|
|
Title:
|
CONTENT-ADDRESSABLE MEMORY (CAM) FOR A FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08974007
|
Filing Dt:
|
11/19/1997
|
|
Title:
|
ROW DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09093943
|
Filing Dt:
|
06/08/1998
|
|
Title:
|
METHOD AND APPARATUS FOR OPERATING ON A MEMORY UNIT VIA A JTAG PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09095808
|
Filing Dt:
|
06/10/1998
|
|
Title:
|
INDIVIDUALLY ACCESSIBLE MACROCELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09097022
|
Filing Dt:
|
06/12/1998
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
GENERAL PORT CAPABLE OF IMPLEMENTING THE JTAG PROTOCOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09178050
|
Filing Dt:
|
10/26/1998
|
|
Title:
|
DUTY CYCLE BASED CHARGE PUMP CONTROLLER
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|
