USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	011967/0805			Pages:	5
		Recorded:	07/12/2001
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 33

Patent #:	4476475	Issue Dt:	10/09/1984	Application #:	06442864	Filing Dt:	11/19/1982
Title:	STACKED MOS TRANSISTOR

Patent #:	4651408	Issue Dt:	03/24/1987	Application #:	06611549	Filing Dt:	05/17/1984
Title:	FABRICATION OF STACKED MOS DEVICES UTILIZING LATERAL SEEDING AND A PLURALITY OF SEPARATE IMPLANTSAT DIFFERENT ENERGIES

Patent #:	4680609	Issue Dt:	07/14/1987	Application #:	06653192	Filing Dt:	09/24/1984
Title:	STRUCTURE AND FABRICATION OF VERTICALLY INTEGRATED CMOS LOGIC GATES

Patent #:	4680854	Issue Dt:	07/21/1987	Application #:	06812993	Filing Dt:	12/24/1985
Title:	FORMING LOW RESISTIVITY HILLOCK FREE CONDUCTORS IN VLSI DEVICES

Patent #:	4683645	Issue Dt:	08/04/1987	Application #:	06813232	Filing Dt:	12/24/1985
Title:	PROCESS OF FABRICATING MOS DEVICES HAVING SHALLOW SOURCE AND DRAIN JUNCTIONS

Patent #:	4745080	Issue Dt:	05/17/1988	Application #:	06831257	Filing Dt:	02/20/1986
Title:	METHOD OF MAKING A SELF ALIGNED BIPOLAQR TRANSISTOR WITH COMPOSITE MASKING

Patent #:	4996081	Issue Dt:	02/26/1991	Application #:	06848609	Filing Dt:	04/07/1986
Title:	METHOD OF FORMING MULTIPLE NITRIDE COATING ON SILICON

Patent #:	4679302	Issue Dt:	07/14/1987	Application #:	06861887	Filing Dt:	05/12/1986
Title:	DOUBLE POLYSILICON INTEGRATED CIRCUIT PROCESS

Patent #:	4718973	Issue Dt:	01/12/1988	Application #:	06864668	Filing Dt:	05/19/1986
Title:	PROCESS FOR PLASMA ETCHING POLYSILICON TO PRODUCE ROUNDED PROFILE ISLANDS

Patent #:	4772571	Issue Dt:	09/20/1988	Application #:	07050467	Filing Dt:	05/18/1987
Title:	A PROCESS OF SELF ALIGNED NITRIDATION OF TISI2 TO FORM TIN/TISI2 CONTACT

Patent #:	4914048	Issue Dt:	04/03/1990	Application #:	07133269	Filing Dt:	12/16/1987
Title:	METHOD OF MAKING BICOMS DEVICES

Patent #:	4849364	Issue Dt:	07/18/1989	Application #:	07133270	Filing Dt:	12/16/1987
Title:	SEMICONDUCTOR DEVICES

Patent #:	4804633	Issue Dt:	02/14/1989	Application #:	07157022	Filing Dt:	02/18/1988
Title:	SILICON-ON-INSULATOR SUBSTRATES ANNEALED IN POLYSILICON TUBE

Patent #:	4868618	Issue Dt:	09/19/1989	Application #:	07174260	Filing Dt:	03/25/1988
Title:	ION IMPLANTED SEMICONDUCTOR DEVICE

Patent #:	5055419	Issue Dt:	10/08/1991	Application #:	07194912	Filing Dt:	05/17/1988
Title:	METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR

Patent #:	4840701	Issue Dt:	06/20/1989	Application #:	07210333	Filing Dt:	06/23/1988
Title:	ETCHING APPARATUS AND METHOD

Patent #:	4916517	Issue Dt:	04/10/1990	Application #:	07282956	Filing Dt:	12/05/1988
Title:	SEMICONDUCTOR DEVICES

Patent #:	4845532	Issue Dt:	07/04/1989	Application #:	07284796	Filing Dt:	12/13/1988
Title:	SEMICONDUCTOR DEVICES

Patent #:	4954214	Issue Dt:	09/04/1990	Application #:	07293789	Filing Dt:	01/05/1989
Title:	METHOD FOR MAKING INTERCONNECT STRUCTURES FOR VLSI DEVICES

Patent #:	4958209	Issue Dt:	09/18/1990	Application #:	07348256	Filing Dt:	05/05/1989
Title:	VARICAP DIODE STRUCTURE

Patent #:	4954865	Issue Dt:	09/04/1990	Application #:	07348258	Filing Dt:	05/05/1989
Title:	INTEGRATED CIRCUITS

Patent #:	4968641	Issue Dt:	11/06/1990	Application #:	07370319	Filing Dt:	06/22/1989
Title:	METHOD FOR FORMATION OF AN ISOLATING OXIDE LAYER

Patent #:	4957873	Issue Dt:	09/18/1990	Application #:	07411196	Filing Dt:	09/21/1989
Title:	PROCESS FOR FORMING ISOLATION FRENCHES IN SILICON SEMICONDUCTOR BODIES

Patent #:	5015600	Issue Dt:	05/14/1991	Application #:	07470027	Filing Dt:	01/25/1990
Title:	METHOD FOR MAKING INTEGRATED CIRCUITS

Patent #:	4965216	Issue Dt:	10/23/1990	Application #:	07471031	Filing Dt:	01/26/1990
Title:	METHOD OF FABRICATING A BI-CMOS DEVICE

Patent #:	5320972	Issue Dt:	06/14/1994	Application #:	08001706	Filing Dt:	01/07/1993
Title:	METHOD OF FORMING A BIPOLAR TRANSISTOR

Patent #:	5428243	Issue Dt:	06/27/1995	Application #:	08158544	Filing Dt:	11/29/1993
Title:	A BIPOLAR TRANSISTOR WITH A SELF-ALIGNED HEAVILY DOPED COLLECTOR REGION AND BASE LINK REGIONS

Patent #:	5422502	Issue Dt:	06/06/1995	Application #:	08163645	Filing Dt:	12/09/1993
Title:	LATERAL BIPOLAR TRANSISTOR

Patent #:	5516708	Issue Dt:	05/14/1996	Application #:	08342041	Filing Dt:	11/17/1994
Title:	METHOD OF MAKING SINGLE POLYSILICON SELF-ALIGNED BIPOLAR TRANSISTOR HAVING REDUCED EMITTER-BASE JUNCTION

Patent #:	5581112	Issue Dt:	12/03/1996	Application #:	08546642	Filing Dt:	10/23/1995
Title:	LATERAL BIPOLAR TRANSISTOR HAVING BURIED BASE CONTACT

Patent #:	5624856	Issue Dt:	04/29/1997	Application #:	08662964	Filing Dt:	06/13/1996
Title:	METHOD FOR FORMING A LATERAL BIPOLAR TRANSISTOR

Patent #:	5686744	Issue Dt:	11/11/1997	Application #:	08665735	Filing Dt:	06/17/1996
Title:	COMPLEMENTARY MODULATION-DOPED FIELD-EFFECT TRANSISTORS

Patent #:	5840596	Issue Dt:	11/24/1998	Application #:	08874253	Filing Dt:	06/13/1997
Title:	METHOD AND MANUFACTURING COMPLEMENTARY MODULATION-DOPED FIELD EFFECT TRANSISTORS

Assignor

NORTEL NETWORKS LIMITED

Exec Dt:

05/25/2001

Assignee

STMICROELECTRONICS N.V.

ROUTE DE PRE-BOIS 20

1215N GENEVA 15, SWITZERLAND

Correspondence name and address
	STMICROELECTRONICS, INC.
	LISA K. JORGENSON
	MAIL STATION 2346
	1310 ELECTRONICS DRIVE
	CARROLLTON, TX 75006

Search Results as of: 05/21/2024 05:54 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6