|
Total properties:
76
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/1983
|
Application #:
|
06355445
|
Filing Dt:
|
04/30/1982
|
|
Title:
|
ION ETCHING PROCESS WITH MINIMIZED REDEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/1984
|
Application #:
|
06397050
|
Filing Dt:
|
07/12/1982
|
|
Title:
|
PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR FET DEVICES AND CONDUCTING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/1985
|
Application #:
|
06397052
|
Filing Dt:
|
07/12/1982
|
|
Title:
|
PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR PET DEVICES AND CONDUCTING LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/1984
|
Application #:
|
06397646
|
Filing Dt:
|
07/12/1982
|
|
Title:
|
HIGH RATE RESIST POLYMERIZATION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1987
|
Application #:
|
06484666
|
Filing Dt:
|
04/13/1983
|
|
Title:
|
DIMENSION MONITORING TECHNIQUE FOR SEMICONDUCTOR FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/1985
|
Application #:
|
06531529
|
Filing Dt:
|
09/12/1983
|
|
Title:
|
METHOD FOR MAKING A RELIABLE OHMIC CONTACT BETWEEN TWO LAYERS OF INTEGRATED CIRCUIT METALLIZATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1987
|
Application #:
|
06831955
|
Filing Dt:
|
02/24/1986
|
|
Title:
|
PRODUCTION OF OXY-METALLO-ORGANIC POLYMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1987
|
Application #:
|
06871655
|
Filing Dt:
|
06/06/1986
|
|
Title:
|
PLANARIZATION PROCESS FOR DOUBLE METAL MOS USING SPIN-ON GLASS AS A SACRIFICIAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/1991
|
Application #:
|
07415827
|
Filing Dt:
|
10/02/1989
|
|
Title:
|
SPENT SOLVENT RECOVERY IN CIRCUIT PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09002326
|
Filing Dt:
|
01/02/1998
|
|
Title:
|
DAMASCENE METALLIZTION PROCESS AND STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09070372
|
Filing Dt:
|
04/30/1998
|
|
Title:
|
APPARAUS FOR REDUCING COOL CHAMBER PARTICLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09149910
|
Filing Dt:
|
09/09/1998
|
|
Title:
|
DUAL-DAMASCENE INTERCONNECT STRUCTURES EMPLOYING LOW-K DIELECTRIC MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09158337
|
Filing Dt:
|
09/22/1998
|
|
Title:
|
INTERCONNECT WITH LOW DIELECTRIC CONSTANT INSULATORS FOR SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
09161176
|
Filing Dt:
|
09/25/1998
|
|
Title:
|
METHODS FOR FORMING HIGH-PERFORMING DUAL-DAMASCENE INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09162185
|
Filing Dt:
|
09/28/1998
|
|
Title:
|
NITRIDE ETCH STOP FOR POISONED UNLANDED VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09162272
|
Filing Dt:
|
09/29/1998
|
|
Title:
|
ELEVATED CHANNEL MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09163135
|
Filing Dt:
|
09/29/1998
|
|
Title:
|
IMPROVED METHODS FOR BARRIER LAYER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09163967
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
IC INTERCONNECT STRUCTURES AND METHODS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09193499
|
Filing Dt:
|
11/16/1998
|
|
Title:
|
INTERCONNECT STRUCTURE AND METHOD EMPLOYING AIR GAPS BETWEEN METAL LINES AND BETWEEN METAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09224339
|
Filing Dt:
|
12/31/1998
|
|
Title:
|
DUAL-DAMASCENE INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09241728
|
Filing Dt:
|
02/02/1999
|
|
Title:
|
THIN-FILM CAPACITORS AND METHODS FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09247234
|
Filing Dt:
|
02/09/1999
|
|
Title:
|
METHODS AND APPARATUS FOR STRIPPING PHOTORESIST AND POLYMER LAYERS FROM A SEMICONDUCTOR STACK IN A NON-CORROSIVE ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09275628
|
Filing Dt:
|
03/24/1999
|
|
Title:
|
METHOD AND APPARATUS FOR HIGH-RESOLUTION IN-SITU PLASMA ETCHING OF INORGANIC AND METAL FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09317536
|
Filing Dt:
|
05/24/1999
|
|
Title:
|
INTERCONNECT WITH LOW DIELECTRIC CONSTANT INSULATORS FOR SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09329569
|
Filing Dt:
|
06/10/1999
|
|
Title:
|
METHOD FOR DUAL DAMASCENE PROCESS USING ELECTRON BEAM AND ION IMPLANTATION CURE METHODS FOR LOW DIELECTRIC CONSTANT MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09369982
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYER AND METHOD FOR ITS FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
09370508
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
ANTI-REFLECTIVE COATING AND PROCESS USING AN ANTI-REFLECTIVE COATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09382003
|
Filing Dt:
|
08/24/1999
|
|
Title:
|
METHOD AND APPARATUS USING FORMIC ACID VAPOR AS REDUCING AGENT FOR COPPER WIREBONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09390445
|
Filing Dt:
|
09/07/1999
|
|
Title:
|
MICROELECTRONIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09411807
|
Filing Dt:
|
10/04/1999
|
|
Title:
|
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09427407
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING SHALLOW TRENCH ISOLATION WITH REDUCED NARROW CHANNEL EFFECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09430729
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE AND PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09432046
|
Filing Dt:
|
11/01/1999
|
|
Title:
|
DIELECTRIC MATERIAL SUITABLE FOR MICROELECTRONIC CIRCUITS AND METHOD OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09465532
|
Filing Dt:
|
12/16/1999
|
|
Title:
|
BONDING PAD AND SUPPORT STRUCTURE AND METHOD FOR THEIR FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09497360
|
Filing Dt:
|
02/03/2000
|
|
Title:
|
PRE-CLEAN CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09512396
|
Filing Dt:
|
02/24/2000
|
|
Title:
|
Method For Fabrication And Structure For High Aspect Ratio Vias
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09512397
|
Filing Dt:
|
02/24/2000
|
|
Title:
|
Method for fabrication of ceramic tantalum nitride and improved structures based thereon
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09559292
|
Filing Dt:
|
04/25/2000
|
|
Title:
|
FABRICATION OF IMPROVED LOW-K DIELECTRIC STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09569890
|
Filing Dt:
|
05/11/2000
|
|
Title:
|
Method for fabrication of damascene interconnects and related structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
09575055
|
Filing Dt:
|
05/19/2000
|
|
Title:
|
METHOD FOR SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09578229
|
Filing Dt:
|
05/24/2000
|
|
Title:
|
STRUCTURE AND METHOD FOR FABRICATION OF AN IMPROVED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09583593
|
Filing Dt:
|
05/31/2000
|
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING A DARK FIELD INSPECTION ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
09590462
|
Filing Dt:
|
06/09/2000
|
|
Title:
|
DOUBLE-IMPLANT HIGH PERFORMANCE VARACTOR AND METHOD FOR MANUFACTURING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09606778
|
Filing Dt:
|
06/28/2000
|
|
Title:
|
Technique for reducing 1/F noise in mosfets
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
09616233
|
Filing Dt:
|
07/14/2000
|
|
Title:
|
ELEVATED CHANNEL MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09627505
|
Filing Dt:
|
07/28/2000
|
|
Title:
|
METHOD FOR FABRICATION OF ON-CHIP INDUCTORS AND RELATED STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09649442
|
Filing Dt:
|
08/25/2000
|
|
Title:
|
METHOD FOR FABRICATION OF HIGH INDUCTANCE INDUCTORS AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09653982
|
Filing Dt:
|
09/01/2000
|
|
Title:
|
BIPOLAR TRANSISTOR WITH REDUCED BASE RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09658483
|
Filing Dt:
|
09/08/2000
|
|
Title:
|
METHOD FOR FABRICATING ON-CHIP INDUCTORS AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
09665422
|
Filing Dt:
|
09/20/2000
|
|
Title:
|
DAMASCENE INTERCONNECT STRUCTURE AND FABRICATION METHOD HAVING AIR GAPS BETWEEN METAL LINES AND METAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09667274
|
Filing Dt:
|
09/22/2000
|
|
Title:
|
Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09667660
|
Filing Dt:
|
09/22/2000
|
|
Title:
|
Method for elimination of contaminants prior to epitaxy
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09668790
|
Filing Dt:
|
09/22/2000
|
|
Title:
|
METHOD FOR INCREASING INDUCTANCE OF ON-CHIP INDUCTORS AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09671928
|
Filing Dt:
|
09/27/2000
|
|
Title:
|
Apparatus for high-resolution in-situ plasma etching of inorganic and metal films
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09677707
|
Filing Dt:
|
09/30/2000
|
|
Title:
|
STRUCTURE FOR REDUCTION OF BASE AND EMITTER RESISTANCE AND RELATED METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09677708
|
Filing Dt:
|
09/30/2000
|
|
Title:
|
METHOD FOR REDUCING CONTAMINATION PRIOR TO EPITAXIAL GROWTH AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
09686323
|
Filing Dt:
|
10/09/2000
|
|
Title:
|
METHOD OF FABRICATING AN INTERCONNECT STRUCTURE EMPLOYING AIR GAPS BETWEEN METAL LINES AND BETWEEN METAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09716350
|
Filing Dt:
|
11/20/2000
|
|
Title:
|
STRUCTURE FOR BONDING PAD AND METHOD FOR ITS FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09721128
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
METHOD FOR FABRICATING INTERFACIAL OXIDE IN A TRANSISTOR AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09721342
|
Filing Dt:
|
11/22/2000
|
|
Title:
|
METHOD FOR FABRICATION OF AN MIM CAPACITOR AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09721344
|
Filing Dt:
|
11/22/2000
|
|
Title:
|
METHOD FOR FABRICATING A SELF-ALIGNED EMITTER IN A BIPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09721551
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
METHOD FOR CONTROLLING CRITICAL DIMENSION IN A POLYCRYSTALLINE SILICON EMITTER AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
09754806
|
Filing Dt:
|
01/02/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/31/2002
| | | | |
|
Title:
|
ON-CHIP INDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09772726
|
Filing Dt:
|
01/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2001
| | | | |
|
Title:
|
Thin-film capacitors and methods for forming the same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09811321
|
Filing Dt:
|
03/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/19/2002
| | | | |
|
Title:
|
HIGH PERFORMANCE BIPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
09833953
|
Filing Dt:
|
04/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
|
Title:
|
LOW COST FABRICATION OF HIGH RESISTIVITY RESISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09850028
|
Filing Dt:
|
05/07/2001
|
|
Title:
|
METHOD FOR REDUCING BASE TO COLLECTOR CAPACITANCE AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09851228
|
Filing Dt:
|
05/08/2001
|
|
Title:
|
METHOD FOR OPENING A SEMICONDUCTOR REGION FOR FABRICATING AN HBT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09852183
|
Filing Dt:
|
05/09/2001
|
|
Title:
|
METHOD TO REDUCE EMITTER TO BASE CAPACITANCE AND RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
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09853735
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Filing Dt:
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05/10/2001
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Title:
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METHOD FOR FABRICATING LATERAL PNP HETEROJUNCTION BIPOLAR TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09955677
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Filing Dt:
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09/19/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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METHOD AND APPARATUS FOR HIGH-RESOLUTION IN-SITU PLASMA ETCHING OF INORGANIC AND METAL FILMS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09967115
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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MICROELECTRONIC AIR-GAP STRUCTURES AND METHODS OF FORMING THE SAME
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10066871
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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BAND GAP COMPENSATED HBT
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10066872
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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METHOD AND STRUCTURE FOR ELIMINATING COLLECTOR-BASE BAND GAP DISCONTINUITY IN AN HBT
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10067034
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Filing Dt:
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02/04/2002
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Title:
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STRUCTURE FOR A SELECTIVE EPITAXIAL HBT EMITTER
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10067159
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Filing Dt:
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02/04/2002
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Title:
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METHOD FOR CONTROLLING CRITICAL DIMENSION IN AN HBT EMITTER AND RELATED STRUCTURE
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