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Reel/Frame:012937/0738   Pages: 15
Recorded: 06/06/2002
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 259
Page 1 of 3
Pages: 1 2 3
1
Patent #:
Issue Dt:
12/19/1978
Application #:
05792940
Filing Dt:
05/02/1977
Title:
PROGRAMMABLE WRITE-ONCE, READ-ONLY SEMICONDUCTOR MEMORY ARRAY WITH IMPROVED CIRCUITRY
2
Patent #:
Issue Dt:
11/07/1978
Application #:
05799509
Filing Dt:
05/23/1977
Title:
PROGRAMMABLE ARRAY LOGIC CIRCUIT
3
Patent #:
Issue Dt:
01/05/1988
Application #:
06433253
Filing Dt:
10/07/1982
Title:
APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT
4
Patent #:
Issue Dt:
12/31/1985
Application #:
06524816
Filing Dt:
08/19/1983
Title:
METHOD AND DEVICE FOR DECODING TWO-DIMENSIONAL FACSIMILE SIGNALS
5
Patent #:
Issue Dt:
09/02/1986
Application #:
06562506
Filing Dt:
12/15/1983
Title:
HIGH CONDUCTANCE CIRCUIT FOR PROGRAMMABLE INTEGRATED CIRCUIT
6
Patent #:
Issue Dt:
08/26/1986
Application #:
06564969
Filing Dt:
12/23/1983
Title:
SEMICONDUCTOR MEMORY DEVICE FOR SERIAL SCAN APPLICATIONS
7
Patent #:
Issue Dt:
03/31/1987
Application #:
06568668
Filing Dt:
01/06/1984
Title:
AN E2 PROM MEMORY CELL
8
Patent #:
Issue Dt:
11/19/1985
Application #:
06575845
Filing Dt:
01/30/1984
Title:
PROGRAMMABLE ARRAY LOGIC CIRCUIT WITH SHARED PRODUCT TERMS
9
Patent #:
Issue Dt:
11/25/1986
Application #:
06621536
Filing Dt:
06/18/1984
Title:
PROGRAMMABLE ARRAY LOGIC CIRCUIT WITH TESTING AND VERIFICATION CIRCUITRY
10
Patent #:
Issue Dt:
01/20/1987
Application #:
06626377
Filing Dt:
06/29/1984
Title:
FAST AND GATE WITH PROGRAMMABLE OUTPUT POLARITY
11
Patent #:
Issue Dt:
02/24/1987
Application #:
06627401
Filing Dt:
07/03/1984
Title:
CURRENT SOURCE WHICH SAVES POWER IN PROGRAMMABLE LOGIC ARRAY CIRCUITRY
12
Patent #:
Issue Dt:
08/04/1987
Application #:
06633164
Filing Dt:
07/20/1984
Title:
PROGRAMMABLE ASYNCHRONOUS REGISTER INITIALIZATION CIRCUIT
13
Patent #:
Issue Dt:
06/02/1987
Application #:
06635861
Filing Dt:
07/30/1984
Title:
SHORT DETECTOR FOR FUSIBLE LINK ARRAY USING A PAIR OF PARALLEL CONNECTED REFERENCE
14
Patent #:
Issue Dt:
02/24/1987
Application #:
06652352
Filing Dt:
09/18/1984
Title:
MULTIPLE PROGRAMMABLE INITIALIZE WORDS IN A PROGRAMMABLE READ ONLY MEMORY
15
Patent #:
Issue Dt:
11/25/1986
Application #:
06663806
Filing Dt:
10/22/1984
Title:
FUSIBLE LINK SHORT DETECTOR WITH ARRAY OF REFERENCE FUSES
16
Patent #:
Issue Dt:
06/02/1987
Application #:
06682381
Filing Dt:
12/17/1984
Title:
PROGRAMMABLE OUTPUT POLARITY DEVICE
17
Patent #:
Issue Dt:
03/31/1987
Application #:
06683078
Filing Dt:
12/18/1984
Title:
EMITTER COUPLED LOGIC BIPOLAR MEMORY CELL
18
Patent #:
Issue Dt:
01/06/1987
Application #:
06683287
Filing Dt:
12/18/1984
Title:
EMITTER COUPLED LOGIC BIPOLAR MEMORY CELL
19
Patent #:
Issue Dt:
03/21/1989
Application #:
06715141
Filing Dt:
03/22/1985
Title:
PROGRAMMABLE LOGIC ARRAY USING EMITTER-COUPLED LOGIC
20
Patent #:
Issue Dt:
08/04/1987
Application #:
06715214
Filing Dt:
03/22/1985
Title:
OUTPUT CIRCUIT FOR A PROGRAMMABLE LOGIC ARRAY
21
Patent #:
Issue Dt:
05/03/1988
Application #:
06717640
Filing Dt:
03/29/1985
Title:
MULTIPLE ARRAY CUSTOMIZABLE LOGIC DEVICE
22
Patent #:
Issue Dt:
05/03/1988
Application #:
06727502
Filing Dt:
04/26/1985
Title:
CMOS ADDRESS TRANSISTION DETECTOR WITH TEMPERATURE COMPENSATION
23
Patent #:
Issue Dt:
01/20/1987
Application #:
06741658
Filing Dt:
06/05/1985
Title:
SHORT DETECTOR FOR FUSIBLE LINK ARRAY USING SINGLE REFERENCE FUSE
24
Patent #:
Issue Dt:
07/19/1988
Application #:
06765038
Filing Dt:
08/12/1985
Title:
PROGRAMMABLE LOGIC ARRAY WITH ADDED ARRAY OF GATES AND ADDED OUTPUT ROUTING FLEXIBILITY
25
Patent #:
Issue Dt:
05/03/1988
Application #:
06780482
Filing Dt:
09/26/1985
Title:
MEMORY CELL HAVING HOT-HOLE INJECTION ERASE MODE
26
Patent #:
Issue Dt:
07/14/1987
Application #:
06794216
Filing Dt:
10/31/1985
Title:
METHOD OF MAKING IMPROVED METAL SILICIDE FUSE FOR INTEGRATED CIRCUIT STRUCTURE
27
Patent #:
Issue Dt:
09/13/1988
Application #:
06795159
Filing Dt:
11/05/1985
Title:
PROGRAMMABLE LOGIC CELL WITH FLEXIBLE CLOCKING AND FLEXIBLE FEEDBACK
28
Patent #:
Issue Dt:
10/24/1989
Application #:
06827840
Filing Dt:
02/07/1986
Title:
LOGIC CONTROLLER HAVING PROGRAMMABLE LOGIC"AND" ARRAY USING A PROGRAMMABLE GRAY-CODE COUNTER
29
Patent #:
Issue Dt:
01/03/1989
Application #:
06852473
Filing Dt:
04/15/1986
Title:
FUSIBLE LINK STRUCTURE FOR INTEGRATED CIRCUITS
30
Patent #:
Issue Dt:
12/06/1988
Application #:
06864185
Filing Dt:
05/16/1986
Title:
PROGRAMMABLE ARRAY LOGIC CELL
31
Patent #:
Issue Dt:
07/19/1988
Application #:
06868970
Filing Dt:
05/30/1986
Title:
PROGRAMMABLE LOGIC DEVICE WITH BURIED REGISTERS SELECTIVELY MULTIPLEXED WITH OUTPUT REGISTERS TO PORTS , AND PRELOAD CIRCUITRY THEREFOR
32
Patent #:
Issue Dt:
10/18/1988
Application #:
06881161
Filing Dt:
07/02/1986
Title:
PROM WITH PROGRAMMABLE OUTPUT STRUCTURES
33
Patent #:
Issue Dt:
04/26/1988
Application #:
06888559
Filing Dt:
07/22/1986
Title:
METHOD FOR FORMING A FUSE
34
Patent #:
Issue Dt:
10/18/1988
Application #:
06891514
Filing Dt:
07/29/1986
Title:
MONOSTABLE LOGIC GATE IN A PROGRAMMABLE LOGIC ARRAY
35
Patent #:
Issue Dt:
02/16/1988
Application #:
06938480
Filing Dt:
12/05/1986
Title:
EMITTER COUPLED LOGIC CIRCUIT HAVING FUSE PROGRAMMABLE LATCH/REGISTER BYPASS
36
Patent #:
Issue Dt:
07/18/1989
Application #:
07047794
Filing Dt:
05/06/1987
Title:
BIPOLAR PROGRAMMABEL LOGIC ARRAY
37
Patent #:
Issue Dt:
12/06/1988
Application #:
07066915
Filing Dt:
06/25/1987
Title:
TEMPERATURE-COMPENSATED INTERFACE CIRCUIT "OR-TIED" CONNECTION OF A PLA DEVICE AND A TTL OUTPUT BUFFER
38
Patent #:
Issue Dt:
09/05/1989
Application #:
07141239
Filing Dt:
01/05/1988
Title:
ECL PROGRAMMABLE LOGIC ARRAY WITH DIRECT TESTING MEANS FOR VERIFICATION OF PROGRAMMED STATE
39
Patent #:
Issue Dt:
08/15/1989
Application #:
07161810
Filing Dt:
02/29/1988
Title:
OUTPUT BUFFER ARRANGEMENT FOR REDUCING CHIP NOISE WITHOUT SPEED PENALTY
40
Patent #:
Issue Dt:
06/05/1990
Application #:
07178707
Filing Dt:
04/07/1988
Title:
MULTIPLE ARRAY CUSTOMIZABLE LOGIC DEVICE
41
Patent #:
Issue Dt:
01/02/1990
Application #:
07193232
Filing Dt:
05/11/1988
Title:
INTEGRATED SCR CURRENT SOURCING SINKING DEVICE
42
Patent #:
Issue Dt:
09/20/1994
Application #:
07207317
Filing Dt:
06/15/1988
Title:
PROGRAMMABLE SYSTEM SYNCHRONIZER
43
Patent #:
Issue Dt:
04/02/1991
Application #:
07207323
Filing Dt:
06/15/1988
Title:
OPTIMIZED ELECTRICALLY ERASABLE PLA CELL FOR MINIMUM READ DISTURB
44
Patent #:
Issue Dt:
07/03/1990
Application #:
07217942
Filing Dt:
07/12/1988
Title:
PROGRAMMABLE LOGIC DEVICE WITH OBSERVABILITY AND PRELOAD CIRCUITRY FOR BURIED STATE REGISTERS
45
Patent #:
Issue Dt:
01/08/1991
Application #:
07227452
Filing Dt:
08/02/1988
Title:
FLEXIBLE, NEXT-ADDRESS GENERATION MICROPROGRAM SEQUENCER
46
Patent #:
Issue Dt:
10/16/1990
Application #:
07243574
Filing Dt:
09/12/1988
Title:
FLEXIBLE, PROGRAMMABLE CELL ARRAY INTERCONNECTED BY A PROGRAMMABLE SWITCH MATRIX
47
Patent #:
Issue Dt:
05/08/1990
Application #:
07274633
Filing Dt:
11/15/1988
Title:
EEPROM USING A MERGED SOURCE AND CONTROL GATE
48
Patent #:
Issue Dt:
04/03/1990
Application #:
07285721
Filing Dt:
12/16/1988
Title:
POLARITY OPTION CONTROL LOGIC FOR USE WITH A REGISTER OF A PROGRAMMABLE LOGIC ARRAY MACROCELL
49
Patent #:
Issue Dt:
08/07/1990
Application #:
07325402
Filing Dt:
03/17/1989
Title:
HIGH SPEED COMPLIMENTARY OUTPUT STAGE UTILIZING CURRENT STEERING TRANSISTORS AND A SINGLE CURRENT SOURCE
50
Patent #:
Issue Dt:
06/12/1990
Application #:
07336628
Filing Dt:
04/10/1989
Title:
OUTPUT CIRCUIT FOR A PROGRAMMABLE LOGIC ARRAY
51
Patent #:
Issue Dt:
06/19/1990
Application #:
07351011
Filing Dt:
06/16/1989
Title:
OPTIMIZED E2 PAL CELL FOR MINIMUM READ DISTURB
52
Patent #:
Issue Dt:
06/12/1990
Application #:
07356107
Filing Dt:
05/24/1989
Title:
METHOD FOR DESIGNING A CONTROL SEQUENCER
53
Patent #:
Issue Dt:
01/12/1993
Application #:
07370148
Filing Dt:
06/21/1989
Title:
PROGRAMMABLE EXPANDABLE CONTROLLER WITH FLEXIBLE I/O
54
Patent #:
Issue Dt:
05/18/1993
Application #:
07394221
Filing Dt:
08/15/1989
Title:
PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE
55
Patent #:
Issue Dt:
06/25/1991
Application #:
07401528
Filing Dt:
08/30/1989
Title:
PROGRAMMABLE LOGIC ARRAY USING INTERNALLY GENERATED DYNAMIC LOGIC SIGNALS AS SELECTION SIGNALS FOR CONTROLLING ITS FUNCTIONS
56
Patent #:
Issue Dt:
01/14/1992
Application #:
07422321
Filing Dt:
10/16/1989
Title:
TEMPERATURE SELF-COMPENSATED TIME DELAY CIRCUITS
57
Patent #:
Issue Dt:
05/21/1991
Application #:
07425306
Filing Dt:
10/23/1989
Title:
METHOD AND APPARATUS FOR PROGRAM VERIFICATION OF A FIELD PROGRAMMABLE LOGIC DEVICE
58
Patent #:
Issue Dt:
08/03/1993
Application #:
07429125
Filing Dt:
10/30/1989
Title:
PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/ OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
59
Patent #:
Issue Dt:
11/09/1993
Application #:
07442528
Filing Dt:
11/27/1989
Title:
PROGRAMMABLE GATE ARRAY WITH IMPROVED CONFIGURABLE LOGIC BLOCK
60
Patent #:
Issue Dt:
08/20/1991
Application #:
07464560
Filing Dt:
01/16/1990
Title:
PROGRAMMABLE LOGIC DEVICE WITH SUBROUTINE STACK AND RANDOM ACCESS MEMORY
61
Patent #:
Issue Dt:
05/14/1991
Application #:
07490808
Filing Dt:
03/07/1990
Title:
MULTIPLE ARRAY HIGH PERFORMANCE PROGRAMMABLE LOGIC DEVICE FAMILY
62
Patent #:
Issue Dt:
07/07/1992
Application #:
07490817
Filing Dt:
03/07/1990
Title:
APPARATUS AND METHOD FOR ALLOCATION OF RESOURCES IN PROGRAMMABLE LOGIC DEVICES
63
Patent #:
Issue Dt:
02/23/1993
Application #:
07500637
Filing Dt:
03/28/1990
Title:
LOW-POWER SENSE AMPLIFIER WITH FEEDBACK
64
Patent #:
Issue Dt:
02/09/1993
Application #:
07503049
Filing Dt:
04/02/1990
Title:
PROGRAMMABNLE GATE ARRAY WITH LOGIC CELLS HAVING CONFIGURABLE OUTPUT ENABLE
65
Patent #:
Issue Dt:
02/19/1991
Application #:
07509649
Filing Dt:
04/16/1990
Title:
TTL-TO-CML TRANSLATOR CIRCUIT
66
Patent #:
Issue Dt:
07/27/1993
Application #:
07514297
Filing Dt:
04/25/1990
Title:
PROGRAMMABLE GATE ARRAY WITH LOGIC CELLS HAVING SYMMETRICAL INPUT/OUTPUT STRUCTURES
67
Patent #:
Issue Dt:
07/27/1993
Application #:
07514520
Filing Dt:
04/25/1990
Title:
APPARATUS AND METHOD FOR IMPROVING THE ENDURANCE OF FLOATING GATE DEVICES
68
Patent #:
Issue Dt:
09/21/1993
Application #:
07520673
Filing Dt:
05/08/1990
Title:
PROGRAMMABLE SENSE AMPLIFIER POWER REDUCTION
69
Patent #:
Issue Dt:
10/19/1993
Application #:
07538211
Filing Dt:
06/14/1990
Title:
INTERCONNECT STRUCTURE FOR PROGRAMMABLE LOGIC DEVICE
70
Patent #:
Issue Dt:
01/07/1992
Application #:
07582013
Filing Dt:
09/13/1990
Title:
SELF-LATCHING LOGIC GATE FOR USE IN PROGRAMMABLE LOGIC ARRAY CIRCUITS
71
Patent #:
Issue Dt:
05/28/1991
Application #:
07584421
Filing Dt:
09/13/1990
Title:
PROGRAMMABLE POWER SUPPLY LEVEL DETECTION AND INITIALIZATION CIRCUITRY
72
Patent #:
Issue Dt:
12/01/1992
Application #:
07603817
Filing Dt:
10/25/1990
Title:
PROGRAMMABLE LOGIC DEVICE WITH OBSERVABILITY AND PRELOADABILITY FOR BURIED STATE REGISTERS
73
Patent #:
Issue Dt:
03/31/1992
Application #:
07604824
Filing Dt:
10/26/1990
Title:
OPTIMIZED ELECTRICALLY ERASABLE CELL FOR MINIMUM READ DISTURB AND ASSOCIATED METHOD OF SENSING
74
Patent #:
Issue Dt:
06/23/1992
Application #:
07655685
Filing Dt:
02/14/1991
Title:
EDGE-TRIGGERED FLIP-FLOP
75
Patent #:
Issue Dt:
07/06/1993
Application #:
07699427
Filing Dt:
05/13/1991
Title:
FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
76
Patent #:
Issue Dt:
03/02/1993
Application #:
07701790
Filing Dt:
05/17/1991
Title:
PROGRAMMABLE LOGIC DEVICE INCORPORATING DIGITAL-TO-ANALOG CONVERTER
77
Patent #:
Issue Dt:
10/06/1992
Application #:
07703455
Filing Dt:
05/21/1991
Title:
PROGRAMMABLE LOGIC DEVICE INCORPORATING VOLTAGE COMPARATOR
78
Patent #:
Issue Dt:
09/21/1993
Application #:
07736205
Filing Dt:
07/26/1991
Title:
PLDS WITH HIGH DRIVE CAPABILITY
79
Patent #:
Issue Dt:
09/29/1992
Application #:
07779547
Filing Dt:
10/18/1991
Title:
PROGRAMMABLE LOGIC DEVICE WITH MULTIPLE, FLEXIBLE ASYNCHRONOUS PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED SWITCH MATRIX
80
Patent #:
Issue Dt:
07/25/1995
Application #:
07816515
Filing Dt:
12/31/1991
Title:
A HIGH SPEED CENTRALIZED SWITCH MATRIX FOR A PROGRAMMABLE LOGIC DEVICE
81
Patent #:
Issue Dt:
11/09/1993
Application #:
07891603
Filing Dt:
06/01/1992
Title:
PROGRAMMABLE, EXPANDABLE CONTROLLER WITH FLEXIBLE I/O
82
Patent #:
Issue Dt:
08/24/1993
Application #:
07897575
Filing Dt:
06/11/1992
Title:
PRECISION TIMING CONTROL PROGRAMMABLE LOGIC DEVICE
83
Patent #:
Issue Dt:
02/06/1996
Application #:
07924201
Filing Dt:
08/03/1992
Title:
FLEXIBLE SYNCHRONOUS/ASYNCHRONOUS CELL STRUCTURE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
84
Patent #:
Issue Dt:
10/10/1995
Application #:
07924685
Filing Dt:
08/03/1992
Title:
ARCHITECTURE OF A MULTIPLE ARRAY HIGH DENSITY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES
85
Patent #:
Issue Dt:
05/24/1994
Application #:
07930969
Filing Dt:
08/13/1992
Title:
PROGRAMMABLE OUTPUT SLEW RATE CONTROL
86
Patent #:
Issue Dt:
11/23/1993
Application #:
08002693
Filing Dt:
01/11/1993
Title:
PROGRAMMABLE VOLTAGE HYSTERESIS ON A VOLTAGE COMPARATOR
87
Patent #:
Issue Dt:
07/12/1994
Application #:
08012573
Filing Dt:
02/01/1993
Title:
PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/ OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
88
Patent #:
Issue Dt:
04/18/1995
Application #:
08017084
Filing Dt:
02/12/1993
Title:
LOW POWER CONSUMPTION AND HIGH SPEED NOR GATE INTEGRATED CIRCUIT
89
Patent #:
Issue Dt:
04/26/1994
Application #:
08024521
Filing Dt:
03/01/1993
Title:
SWITCH MATRIX MULTIPLEXERS
90
Patent #:
Issue Dt:
10/25/1994
Application #:
08025551
Filing Dt:
03/03/1993
Title:
PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
91
Patent #:
Issue Dt:
04/11/1995
Application #:
08034510
Filing Dt:
03/19/1993
Title:
INPUT BUFFER UTILIZING A CASCODE TO PROVIDE A ZERO POWER TTL TO CMOS INPUT WITH HIGH SPEED SWITCHING
92
Patent #:
Issue Dt:
11/21/1995
Application #:
08034537
Filing Dt:
03/19/1993
Title:
CASCADE ARRAY CELL PARTITIONING FOR A SENSE AMPLIFIER OF A PROGRAMMABLE LOGIC DEVICE
93
Patent #:
Issue Dt:
08/01/1995
Application #:
08034549
Filing Dt:
03/19/1993
Title:
GROUND BOUNCE ISOLATED OUTPUT BUFFER
94
Patent #:
Issue Dt:
07/01/1997
Application #:
08080658
Filing Dt:
06/18/1993
Title:
PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES
95
Patent #:
Issue Dt:
06/20/1995
Application #:
08085601
Filing Dt:
06/30/1993
Title:
PINOUT ARCHITECTURE FOR A FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
96
Patent #:
Issue Dt:
07/25/1995
Application #:
08118123
Filing Dt:
09/07/1993
Title:
INPUT TRANSITION DETECTION CIRCUIT FOR ZERO-POWER PART
97
Patent #:
Issue Dt:
04/25/1995
Application #:
08118432
Filing Dt:
09/08/1993
Title:
LATCHING ZERO-POWER SENSE AMPLIFIER WITH CASCODE
98
Patent #:
Issue Dt:
10/10/1995
Application #:
08118801
Filing Dt:
09/08/1993
Title:
ZERO-POWER OR GATE
99
Patent #:
Issue Dt:
08/01/1995
Application #:
08128628
Filing Dt:
09/28/1993
Title:
HIGH SPEED CMOS OUTPUT BUFFER CIRCUIT MINIMIZES PROPAGATION DELAY AND CROWBAR CURRENT
100
Patent #:
Issue Dt:
05/23/1995
Application #:
08134523
Filing Dt:
10/08/1993
Title:
INPUT LEVEL DETECTION CIRCUIT
Assignor
1
Exec Dt:
02/11/2002
Assignee
1
5555 NE MOORE COURT
HILLSBORO, OREGON 97124
Correspondence name and address
MARK L. BECKER
5555 NE MOORE COURT
HILLSBORO, OR 97124

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