Total properties:
37
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Patent #:
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Issue Dt:
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06/06/1989
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Application #:
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07038107
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Filing Dt:
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04/14/1987
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Title:
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COUNTING RAM
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Patent #:
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Issue Dt:
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03/20/1990
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Application #:
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07191305
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Filing Dt:
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05/06/1988
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Title:
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METHOD TO REDUCE SILICON AREA FOR VIA FORMATION
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Patent #:
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Issue Dt:
|
02/12/1991
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Application #:
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07255074
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Filing Dt:
|
10/07/1988
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Title:
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RESISTOR WITH SIDE WALL CONTACT
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Patent #:
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Issue Dt:
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05/12/1992
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Application #:
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07294318
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Filing Dt:
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01/06/1989
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Title:
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CONTACTLESS NON-VOLATILE MEMORY ARRAY CELLS
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Patent #:
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Issue Dt:
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08/03/1993
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Application #:
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07325554
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Filing Dt:
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03/17/1989
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Title:
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EXPANDED CACHE MEMORY SYSTEM
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Patent #:
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Issue Dt:
|
03/19/1991
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Application #:
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07372072
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Filing Dt:
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06/27/1989
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Title:
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CONTROLLER FOR DUAL PORTED MEMORY
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Patent #:
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Issue Dt:
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05/28/1991
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Application #:
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07429580
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Filing Dt:
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10/31/1989
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Title:
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PROCESS OF MAKING SELF-ALIGNED CONTACT DIFFERENTIAL OXIDATION
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Patent #:
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Issue Dt:
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01/28/1992
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Application #:
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07479905
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Filing Dt:
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02/14/1990
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Title:
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RESISTOR WITH SIDE WALL CONTACT
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Patent #:
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Issue Dt:
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09/29/1992
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Application #:
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07609836
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Filing Dt:
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11/06/1990
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Title:
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CMOS LOGIC CIRCUIT WITH OUTPUT COUPLED TO MULTIPLE FEEDBACK PATHS AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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06/23/1992
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Application #:
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07642077
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Filing Dt:
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01/16/1991
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Title:
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PULSED BOOTSTRAPPING OUTPUT BUFFER AND ASSOCIATED METHOD
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|
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Patent #:
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Issue Dt:
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01/30/1996
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Application #:
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07678912
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Filing Dt:
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04/01/1991
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Title:
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CACHE INCLUDING DECOUPLING REGISTER CIRCUITS
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Patent #:
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|
Issue Dt:
|
09/14/1993
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Application #:
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07679511
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Filing Dt:
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04/02/1991
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Title:
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INTEGRATED CIRCUIT MEMORY WITH DECODED ADDRESS SUSTAIN CIRCUITRY FOR MULTIPLEXED ADDRESS ARCHITECTURE AND METHOD
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Patent #:
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Issue Dt:
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09/20/1994
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Application #:
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07755319
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Filing Dt:
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09/05/1991
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Title:
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SRAM WITH TRANSPARENT ADDRESS LATCH AND UNLATCHED CHIP ENABLE
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Patent #:
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Issue Dt:
|
11/09/1993
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Application #:
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07835167
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Filing Dt:
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02/13/1992
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Title:
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DIGITAL COMPARATOR CIRCUIT
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Patent #:
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Issue Dt:
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09/28/1993
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Application #:
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07843841
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Filing Dt:
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02/28/1992
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Title:
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SRAM WITH AN ADDRESS AND DATA MULTIPLEXER
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|
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Patent #:
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Issue Dt:
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09/20/1994
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Application #:
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07916304
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Filing Dt:
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07/16/1992
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Title:
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BIDIRECTIONAL FIFO WITH PARITY GENERATOR/CHECKER
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|
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Patent #:
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|
Issue Dt:
|
08/22/1995
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Application #:
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08067409
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Filing Dt:
|
05/25/1993
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Title:
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DOPANT-DIFFUSION BUFFERED BURIED CONTACT MODULE FOR INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
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03/24/1998
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Application #:
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08170642
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Filing Dt:
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12/20/1993
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Title:
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RANDOM ACCESS CACHE MEMORY CONTROLLER AND SYSTEM
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|
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Patent #:
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|
Issue Dt:
|
09/19/1995
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Application #:
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08265535
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Filing Dt:
|
06/24/1994
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Title:
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SERIAL ADDRESS GENERATOR FOR BURST MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
06/16/1998
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Application #:
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08695058
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Filing Dt:
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08/09/1996
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Title:
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METHODS AND APPARATUS FOR CHARGING A SENSE AMPLIFIER
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|
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Patent #:
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|
Issue Dt:
|
06/02/1998
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Application #:
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08717031
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Filing Dt:
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09/20/1996
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Title:
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CHARGE STORAGE FOR SENSING OPERATIONS IN A DRAM
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|
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Patent #:
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|
Issue Dt:
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12/01/1998
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Application #:
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08717471
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Filing Dt:
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09/20/1996
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Title:
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SPACE SAVING LASER PROGRAMMABLE FUSE LAYOUT
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|
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Patent #:
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|
Issue Dt:
|
09/22/1998
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Application #:
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08733858
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Filing Dt:
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10/18/1996
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Title:
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I/O BIAS CIRCUIT INSENSITIVE TO INADVERTENT POWER SUPPLY VARIATIONS FOR MOS MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
06/16/1998
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Application #:
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08760121
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Filing Dt:
|
12/03/1996
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Title:
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CHARGING A SENSE AMPLIFIER
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/1998
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Application #:
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08760124
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Filing Dt:
|
12/03/1996
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Title:
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DRAM WITH STAGGERED SHARED BIT LINE SENSE AMPLIFIER ARCHITECTURE
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|
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Patent #:
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|
Issue Dt:
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10/27/1998
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Application #:
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08760125
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Filing Dt:
|
12/03/1996
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Title:
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SIMULATED DRAM MEMORY BIT LINE/BIT LINE FOR CIRCUIT TIMING AND VOLTAGE LEVEL TRACKING
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|
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Patent #:
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|
Issue Dt:
|
11/17/1998
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Application #:
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08805391
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Filing Dt:
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02/24/1997
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Title:
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INTRACHIP POWER DISTRIBUTION PACKAGE AND METHOD FOR SEMICONDUCTORS HAVING A SUPPLY NODE ELECTRICALLY INTERCONNECTED WITH ONE OR MORE INTERMEDIATE NODES
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|
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Patent #:
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|
Issue Dt:
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03/30/1999
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Application #:
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08840337
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Filing Dt:
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04/28/1997
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Title:
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PROGRAMMABLE CIRCUITS
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|
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Patent #:
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|
Issue Dt:
|
07/14/1998
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Application #:
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08844541
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Filing Dt:
|
04/18/1997
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Title:
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DRAM WITH NEW I/O DATA PATH CONFIGURATION
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|
|
Patent #:
|
|
Issue Dt:
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11/17/1998
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Application #:
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08850933
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Filing Dt:
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02/28/1997
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Title:
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RECONFIGURABLE MULTIPLEXED ADDRESS SCHEME FOR ASYMMETRICALLY ADDRESSED DRAMS
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|
|
Patent #:
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|
Issue Dt:
|
05/25/1999
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Application #:
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08853291
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Filing Dt:
|
05/09/1997
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Title:
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GENERATION OF SIGNALS FROM OTHER SIGNALS THAT TAKE TIME TO DEVELOP ON POWER-UP
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|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
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Application #:
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08947776
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Filing Dt:
|
10/09/1997
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Title:
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USING THE INTERNAL SUPPLY VOLTAGE RAMP RATE TO PREVENT PREMATURE ENABLING OF A DEVICE DURING POWER-UP
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|
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Patent #:
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|
Issue Dt:
|
01/04/2000
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Application #:
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08967436
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Filing Dt:
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11/11/1997
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Title:
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DRAM WITH EDGE SENSE AMPLIFIERS WHICH ARE ACTIVATED ALONG WITH SENSE AMPLIFIERS INTERNAL TO THE ARRAY DURING A READ CYCLE
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|
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Patent #:
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|
Issue Dt:
|
10/12/1999
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Application #:
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09047304
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Filing Dt:
|
03/24/1998
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Title:
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DRAM WITH NEW I/O DATA PATH CONFIGURATI0N
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|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
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Application #:
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09062175
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Filing Dt:
|
04/16/1998
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Title:
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I/O BIAS CIRCUIT INSENSITIVE TO INADVERTENT POWER SUPPLY VARIATIONS FOR MOS MEMORY
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|
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Patent #:
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|
Issue Dt:
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09/28/1999
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Application #:
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09139538
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Filing Dt:
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08/25/1998
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Title:
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SEMICONDUCTOR MEMORY HAVING SINGLE PATH DATA PIPELINE FOR CAS-LATENCY
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|
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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09153787
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Filing Dt:
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09/16/1998
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Title:
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SEMICONDUCTOR MEMORY HAVING PREDECODER CONTROL OF SPARE COLUMN SELECT LINES
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