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Patent Assignment Details
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Reel/Frame:016686/0825   Pages: 3
Recorded: 06/20/2005
Attorney Dkt #:20003-013
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 37
1
Patent #:
Issue Dt:
06/06/1989
Application #:
07038107
Filing Dt:
04/14/1987
Title:
COUNTING RAM
2
Patent #:
Issue Dt:
03/20/1990
Application #:
07191305
Filing Dt:
05/06/1988
Title:
METHOD TO REDUCE SILICON AREA FOR VIA FORMATION
3
Patent #:
Issue Dt:
02/12/1991
Application #:
07255074
Filing Dt:
10/07/1988
Title:
RESISTOR WITH SIDE WALL CONTACT
4
Patent #:
Issue Dt:
05/12/1992
Application #:
07294318
Filing Dt:
01/06/1989
Title:
CONTACTLESS NON-VOLATILE MEMORY ARRAY CELLS
5
Patent #:
Issue Dt:
08/03/1993
Application #:
07325554
Filing Dt:
03/17/1989
Title:
EXPANDED CACHE MEMORY SYSTEM
6
Patent #:
Issue Dt:
03/19/1991
Application #:
07372072
Filing Dt:
06/27/1989
Title:
CONTROLLER FOR DUAL PORTED MEMORY
7
Patent #:
Issue Dt:
05/28/1991
Application #:
07429580
Filing Dt:
10/31/1989
Title:
PROCESS OF MAKING SELF-ALIGNED CONTACT DIFFERENTIAL OXIDATION
8
Patent #:
Issue Dt:
01/28/1992
Application #:
07479905
Filing Dt:
02/14/1990
Title:
RESISTOR WITH SIDE WALL CONTACT
9
Patent #:
Issue Dt:
09/29/1992
Application #:
07609836
Filing Dt:
11/06/1990
Title:
CMOS LOGIC CIRCUIT WITH OUTPUT COUPLED TO MULTIPLE FEEDBACK PATHS AND ASSOCIATED METHOD
10
Patent #:
Issue Dt:
06/23/1992
Application #:
07642077
Filing Dt:
01/16/1991
Title:
PULSED BOOTSTRAPPING OUTPUT BUFFER AND ASSOCIATED METHOD
11
Patent #:
Issue Dt:
01/30/1996
Application #:
07678912
Filing Dt:
04/01/1991
Title:
CACHE INCLUDING DECOUPLING REGISTER CIRCUITS
12
Patent #:
Issue Dt:
09/14/1993
Application #:
07679511
Filing Dt:
04/02/1991
Title:
INTEGRATED CIRCUIT MEMORY WITH DECODED ADDRESS SUSTAIN CIRCUITRY FOR MULTIPLEXED ADDRESS ARCHITECTURE AND METHOD
13
Patent #:
Issue Dt:
09/20/1994
Application #:
07755319
Filing Dt:
09/05/1991
Title:
SRAM WITH TRANSPARENT ADDRESS LATCH AND UNLATCHED CHIP ENABLE
14
Patent #:
Issue Dt:
11/09/1993
Application #:
07835167
Filing Dt:
02/13/1992
Title:
DIGITAL COMPARATOR CIRCUIT
15
Patent #:
Issue Dt:
09/28/1993
Application #:
07843841
Filing Dt:
02/28/1992
Title:
SRAM WITH AN ADDRESS AND DATA MULTIPLEXER
16
Patent #:
Issue Dt:
09/20/1994
Application #:
07916304
Filing Dt:
07/16/1992
Title:
BIDIRECTIONAL FIFO WITH PARITY GENERATOR/CHECKER
17
Patent #:
Issue Dt:
08/22/1995
Application #:
08067409
Filing Dt:
05/25/1993
Title:
DOPANT-DIFFUSION BUFFERED BURIED CONTACT MODULE FOR INTEGRATED CIRCUITS
18
Patent #:
Issue Dt:
03/24/1998
Application #:
08170642
Filing Dt:
12/20/1993
Title:
RANDOM ACCESS CACHE MEMORY CONTROLLER AND SYSTEM
19
Patent #:
Issue Dt:
09/19/1995
Application #:
08265535
Filing Dt:
06/24/1994
Title:
SERIAL ADDRESS GENERATOR FOR BURST MEMORY
20
Patent #:
Issue Dt:
06/16/1998
Application #:
08695058
Filing Dt:
08/09/1996
Title:
METHODS AND APPARATUS FOR CHARGING A SENSE AMPLIFIER
21
Patent #:
Issue Dt:
06/02/1998
Application #:
08717031
Filing Dt:
09/20/1996
Title:
CHARGE STORAGE FOR SENSING OPERATIONS IN A DRAM
22
Patent #:
Issue Dt:
12/01/1998
Application #:
08717471
Filing Dt:
09/20/1996
Title:
SPACE SAVING LASER PROGRAMMABLE FUSE LAYOUT
23
Patent #:
Issue Dt:
09/22/1998
Application #:
08733858
Filing Dt:
10/18/1996
Title:
I/O BIAS CIRCUIT INSENSITIVE TO INADVERTENT POWER SUPPLY VARIATIONS FOR MOS MEMORY
24
Patent #:
Issue Dt:
06/16/1998
Application #:
08760121
Filing Dt:
12/03/1996
Title:
CHARGING A SENSE AMPLIFIER
25
Patent #:
Issue Dt:
05/26/1998
Application #:
08760124
Filing Dt:
12/03/1996
Title:
DRAM WITH STAGGERED SHARED BIT LINE SENSE AMPLIFIER ARCHITECTURE
26
Patent #:
Issue Dt:
10/27/1998
Application #:
08760125
Filing Dt:
12/03/1996
Title:
SIMULATED DRAM MEMORY BIT LINE/BIT LINE FOR CIRCUIT TIMING AND VOLTAGE LEVEL TRACKING
27
Patent #:
Issue Dt:
11/17/1998
Application #:
08805391
Filing Dt:
02/24/1997
Title:
INTRACHIP POWER DISTRIBUTION PACKAGE AND METHOD FOR SEMICONDUCTORS HAVING A SUPPLY NODE ELECTRICALLY INTERCONNECTED WITH ONE OR MORE INTERMEDIATE NODES
28
Patent #:
Issue Dt:
03/30/1999
Application #:
08840337
Filing Dt:
04/28/1997
Title:
PROGRAMMABLE CIRCUITS
29
Patent #:
Issue Dt:
07/14/1998
Application #:
08844541
Filing Dt:
04/18/1997
Title:
DRAM WITH NEW I/O DATA PATH CONFIGURATION
30
Patent #:
Issue Dt:
11/17/1998
Application #:
08850933
Filing Dt:
02/28/1997
Title:
RECONFIGURABLE MULTIPLEXED ADDRESS SCHEME FOR ASYMMETRICALLY ADDRESSED DRAMS
31
Patent #:
Issue Dt:
05/25/1999
Application #:
08853291
Filing Dt:
05/09/1997
Title:
GENERATION OF SIGNALS FROM OTHER SIGNALS THAT TAKE TIME TO DEVELOP ON POWER-UP
32
Patent #:
Issue Dt:
06/15/1999
Application #:
08947776
Filing Dt:
10/09/1997
Title:
USING THE INTERNAL SUPPLY VOLTAGE RAMP RATE TO PREVENT PREMATURE ENABLING OF A DEVICE DURING POWER-UP
33
Patent #:
Issue Dt:
01/04/2000
Application #:
08967436
Filing Dt:
11/11/1997
Title:
DRAM WITH EDGE SENSE AMPLIFIERS WHICH ARE ACTIVATED ALONG WITH SENSE AMPLIFIERS INTERNAL TO THE ARRAY DURING A READ CYCLE
34
Patent #:
Issue Dt:
10/12/1999
Application #:
09047304
Filing Dt:
03/24/1998
Title:
DRAM WITH NEW I/O DATA PATH CONFIGURATI0N
35
Patent #:
Issue Dt:
09/07/1999
Application #:
09062175
Filing Dt:
04/16/1998
Title:
I/O BIAS CIRCUIT INSENSITIVE TO INADVERTENT POWER SUPPLY VARIATIONS FOR MOS MEMORY
36
Patent #:
Issue Dt:
09/28/1999
Application #:
09139538
Filing Dt:
08/25/1998
Title:
SEMICONDUCTOR MEMORY HAVING SINGLE PATH DATA PIPELINE FOR CAS-LATENCY
37
Patent #:
Issue Dt:
09/21/1999
Application #:
09153787
Filing Dt:
09/16/1998
Title:
SEMICONDUCTOR MEMORY HAVING PREDECODER CONTROL OF SPARE COLUMN SELECT LINES
Assignor
1
Exec Dt:
06/14/2005
Assignee
1
3F, NO. 19, LI-HSIN ROAD
SCIENCE-BASED INDUSTRIAL PARK
HSIN CHU CITY, TAIWAN
Correspondence name and address
MICHAEL SHENKER
MACPHERSON, KWOK CHEN & HEID LLP
1762 TECHNOLOGY DRIVE
SUITE 226
SAN JOSE, CA 95110

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