|
Total properties:
54
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|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11351058
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Filing Dt:
|
02/09/2006
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|
Publication #:
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Pub Dt:
|
06/07/2007
| | | | |
|
Title:
|
SMALL AND POWER-EFFICIENT CACHE THAT CAN PROVIDE DATA FOR BACKGROUND DMA DEVICES WHILE THE PROCESSOR IS IN A LOW-POWER STATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11351070
|
Filing Dt:
|
02/09/2006
|
|
Publication #:
|
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Pub Dt:
|
05/17/2007
| | | | |
|
Title:
|
POWER CONSERVATION VIA DRAM ACCESS REDUCTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11408784
|
Filing Dt:
|
04/21/2006
|
|
Title:
|
REDUCING POWER CONSUMPTION FOR PROCESSING OF COMMON VALUES IN MICROPROCESSOR REGISTERS AND EXECUTION UNITS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11416872
|
Filing Dt:
|
05/02/2006
|
|
Title:
|
SYSTEM AND METHOD FOR OPTIMIZING A MEMORY CONTROLLER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11450103
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Filing Dt:
|
06/09/2006
|
|
Title:
|
SYSTEM AND METHOD FOR CONSERVING POWER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11543598
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Filing Dt:
|
10/04/2006
|
|
Title:
|
CACHE OPERATIONS WITH HIERARCHY CONTROL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11555253
|
Filing Dt:
|
10/31/2006
|
|
Publication #:
|
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Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
DYNAMIC RESOURCE ALLOCATION AMONG MASTER PROCESSORS THAT REQUIRE SERVICE FROM A COPROCESSOR
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|
|
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Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11555258
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Filing Dt:
|
10/31/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
SYNCHRONIZING MASTER PROCESSOR BY STALLING WHEN TRACKING OF COPROCESSOR RENAME REGISTER RESOURCE USAGE COUNT FOR SENT INSTRUCTIONS REACHES CREDITED APPORTIONED NUMBER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11555263
|
Filing Dt:
|
10/31/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
COPROCESSOR RECEIVING RENAMED REGISTER IDENTIFIER FROM MASTER TO COMPLETE AN OPERATION UPON REGISTER DATA READY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
11559069
|
Filing Dt:
|
11/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
|
Title:
|
SMALL AND POWER-EFFICIENT CACHE THAT CAN PROVIDE DATA FOR BACKGROUND DMA DEVICES WHILE THE PROCESSOR IS IN A LOW-POWER STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11559133
|
Filing Dt:
|
11/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2007
| | | | |
|
Title:
|
POWER CONSERVATION VIA DRAM ACCESS REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
11559192
|
Filing Dt:
|
11/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
|
Title:
|
POWER CONSERVATION VIA DRAM ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11591024
|
Filing Dt:
|
10/31/2006
|
|
Title:
|
MAINTAINING MEMORY COHERENCY WITH A TRACE CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11646008
|
Filing Dt:
|
12/26/2006
|
|
Title:
|
PREDICTION OF DATA VALUES READ FROM MEMORY BY A MICROPROCESSOR USING THE STORAGE DESTINATION OF A LOAD OPERATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11737103
|
Filing Dt:
|
04/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
NAND/NOR REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11738287
|
Filing Dt:
|
04/20/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
DYNAMIC DUAL OUTPUT LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
11745370
|
Filing Dt:
|
05/07/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
|
Title:
|
ENHANCED SIGNALING SENSITIVITY USING MULTIPLE REFERENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11764159
|
Filing Dt:
|
06/15/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
|
Title:
|
SYMMETRICAL DIFFERENTIAL AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11777074
|
Filing Dt:
|
07/12/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
|
Title:
|
MEMORY CELLS WITH POWER SWITCH CIRCUIT FOR IMPROVED LOW VOLTAGE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11781726
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
VIRTUAL CORE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
11782163
|
Filing Dt:
|
07/24/2007
|
|
Title:
|
SYSTEM AND METHOD FOR ENSURING COHERENCY IN TRACE EXECUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11782238
|
Filing Dt:
|
07/24/2007
|
|
Title:
|
METHOD AND SYSTEM FOR UTILIZING A COMMON STRUCTURE FOR TRACE VERIFICATION AND MAINTAINING COHERENCY IN AN INSTRUCTION PROCESSING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11880859
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
CONCURRENT VS. LOW POWER BRANCH PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11880861
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
TRACE UNIT WITH A TRACE BUILDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
11880862
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
TRACE UNIT WITH A DECODER, A BASIC-BLOCK CACHE, A MULTI-BLOCK CACHE, AND SEQUENCER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
11880863
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
TRACE UNIT WITH AN OP PATH FROM A DECODER (BYPASS MODE) AND FROM A BASIC-BLOCK BUILDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
11880875
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
INSTRUCTION CACHE, DECODER CIRCUIT, BASIC BLOCK CACHE CIRCUIT AND MULTI-BLOCK CACHE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
11880882
|
Filing Dt:
|
07/23/2007
|
|
Title:
|
TRACE UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11923638
|
Filing Dt:
|
10/24/2007
|
|
Title:
|
GRACEFUL DEGRADATION IN A TRACE-BASED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11923640
|
Filing Dt:
|
10/24/2007
|
|
Title:
|
ABORT PRIORITIZATION IN A TRACE-BASED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
11932311
|
Filing Dt:
|
10/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
|
Title:
|
DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
11932555
|
Filing Dt:
|
10/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
MEMORY DEVICE WITH SPLIT POWER SWITCH
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11932643
|
Filing Dt:
|
10/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
METHOD OF SELECTIVELY POWERING MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11932738
|
Filing Dt:
|
10/31/2007
|
|
Title:
|
METHOD OF OPERATING MEMORY CELL PROVIDING INTERNAL POWER SWITCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11932967
|
Filing Dt:
|
10/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
|
Title:
|
ELASTIC POWER FOR READ AND WRITE MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
11933267
|
Filing Dt:
|
10/31/2007
|
|
Title:
|
VIRTUAL CORE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11933297
|
Filing Dt:
|
10/31/2007
|
|
Title:
|
VIRTUAL CORE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
11933319
|
Filing Dt:
|
10/31/2007
|
|
Title:
|
VIRTUAL CORE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
11933349
|
Filing Dt:
|
10/31/2007
|
|
Title:
|
VIRTUAL CORE MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11938196
|
Filing Dt:
|
11/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
|
Title:
|
ELASTIC POWER FOR READ MARGIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
11941883
|
Filing Dt:
|
11/16/2007
|
|
Title:
|
PROMOTING AND APPENDING TRACES IN AN INSTRUCTION PROCESSING CIRCUIT BASED UPON A BIAS VALUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11941900
|
Filing Dt:
|
11/16/2007
|
|
Title:
|
FLAG OPTIMIZATION OF A TRACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11941908
|
Filing Dt:
|
11/16/2007
|
|
Title:
|
EMIT VECTOR OPTIMIZATION OF A TRACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
11941912
|
Filing Dt:
|
11/16/2007
|
|
Title:
|
SYMBOLIC RENAMING OPTIMIZATION OF A TRACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
11963579
|
Filing Dt:
|
12/21/2007
|
|
Title:
|
MICROPROCESSOR INCLUDING A DISPLAY INTERFACE IN THE MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
11963603
|
Filing Dt:
|
12/21/2007
|
|
Title:
|
MICROPROCESSOR INCLUDING A DISPLAY INTERFACE IN THE MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12030846
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
TRACE BASED DEALLOCATION OF ENTRIES IN A VERSIONING CACHE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12030851
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
MEMORY ORDERING QUEUE/VERSIONING CACHE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12030852
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
TRACE BASED ROLLBACK OF A SPECULATIVELY UPDATED CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12030854
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
DATA CACHE ROLLBACKS FOR FAILED SPECULATIVE TRACES WITH MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12030857
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
MEMORY ORDERING QUEUE TIGHTLY COUPLED WITH A VERSIONING CACHE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12030858
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
CACHE ROLLBACK ACCELERATION VIA A BANK BASED VERSIONING CACHE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12030859
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
ROLLING BACK A SPECULATIVE UPDATE OF A NON-MODIFIABLE CACHE LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12030862
|
Filing Dt:
|
02/13/2008
|
|
Title:
|
CHECKING FOR A MEMORY ORDERING VIOLATION AFTER A SPECULATIVE CACHE WRITE
|
|
