|
Total properties:
15
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11388326
|
Filing Dt:
|
03/23/2006
|
|
Title:
|
METHOD AND APPARATUS FOR PARALLEL CARRY CHAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
11400590
|
Filing Dt:
|
04/07/2006
|
|
Title:
|
INCREMENTAL MODIFICATION OF INSTRUMENTATION LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11417355
|
Filing Dt:
|
05/02/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DEBUGGING AN ELECTRONIC SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11491437
|
Filing Dt:
|
07/21/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS OF MULTI-CHANNEL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
11601411
|
Filing Dt:
|
11/17/2006
|
|
Title:
|
METHODS AND APPARATUSES FOR RESET CONDITIONING IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
11605554
|
Filing Dt:
|
11/27/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CIRCUIT DESIGN AND RETIMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
11637360
|
Filing Dt:
|
12/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11698330
|
Filing Dt:
|
01/25/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
|
Title:
|
POWER AND GROUND SHIELD MESH TO REMOVE BOTH CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS OF ROUTING IN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11700685
|
Filing Dt:
|
01/30/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS OF MULTI-CHANNEL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11726777
|
Filing Dt:
|
03/22/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
|
Title:
|
METHODS AND SYSTEMS FOR OPTIMIZING DESIGNS OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
11732784
|
Filing Dt:
|
04/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2007
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
11762024
|
Filing Dt:
|
06/12/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CIRCUIT PARTITIONING AND TRACE ASSIGNMENT IN CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11786865
|
Filing Dt:
|
04/13/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
HARDWARE-BASED HDL CODE COVERAGE AND DESIGN ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11809613
|
Filing Dt:
|
05/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
|
Title:
|
METHODS AND APPARATUSES FOR DESIGNING MULTIPLEXERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11809700
|
Filing Dt:
|
05/31/2007
|
|
Title:
|
ENHANCED HARDWARE DEBUGGING WITH EMBEDDED FPGAS IN A HARDWARE DESCRIPTION LANGUAGE
|
|
