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Patent #:
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Issue Dt:
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05/30/1989
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Application #:
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07121612
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Filing Dt:
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11/17/1987
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Title:
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METHOD AND APPARATUS FOR SIGNAL LEVEL CONVERSION WITH CLAMPED CAPACITIVE BOOTSTRAP
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Patent #:
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Issue Dt:
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10/24/1989
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Application #:
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07164556
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Filing Dt:
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03/07/1988
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING PROCESS PROVIDING OXIDE-FILLED TRENCH ISOLATION OF CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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10/17/1989
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Application #:
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07193261
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Filing Dt:
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05/11/1988
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Title:
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ECL OUTPUT WITH DARLINGTON OR COMMON COLLECTOR-COMMON EMITTER DRIVE
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Patent #:
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Issue Dt:
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07/04/1989
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Application #:
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07209433
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Filing Dt:
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06/21/1988
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Title:
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BICMOS LOGIC CIRCUITS WITH REDUCED CROWBAR CURRENT
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Patent #:
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Issue Dt:
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05/15/1990
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Application #:
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07240136
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Filing Dt:
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09/02/1988
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Title:
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METHOD AND APPARATUS FOR COUPLING AN ECL OUTPUT SIGNAL USING A CLAMPED CAPACITIVE BOOTSTRAP CIRCUIT
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Patent #:
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Issue Dt:
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10/17/1989
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Application #:
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07314510
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Filing Dt:
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02/21/1989
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Title:
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NON-CONTACT I/O SIGNAL PAD SCAN TESTING OF VLSI CIRCUITS
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Patent #:
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Issue Dt:
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11/13/1990
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Application #:
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07376608
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Filing Dt:
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07/07/1989
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Title:
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TTL-LEVEL-OUTPUT INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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09/10/1991
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Application #:
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07397768
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Filing Dt:
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08/23/1989
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Title:
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WAFER-LEVEL BURN-IN TESTING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/08/1995
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Application #:
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08109805
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Filing Dt:
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08/19/1993
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Title:
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MULTIPLE-PORT SHARED MEMORY INTERFACE AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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08512613
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Filing Dt:
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08/07/1995
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Title:
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MEMORY INTERFACE UNIT, SHARED MEMORY SWITCH SYSTEM AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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01/02/2001
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Application #:
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08959636
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Filing Dt:
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10/28/1997
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Title:
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ACCESSING A MEMORY SYSTEM VIA A DATA OR ADDRESS BUS THAT PROVIDES ACCESS TO MORE THAN ONE PORT
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Patent #:
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Issue Dt:
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06/08/1999
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Application #:
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08998586
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Filing Dt:
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12/29/1997
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Title:
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MEMORY INTERFACE UNIT, SHARED MEMORY SWITCH SYSTEM AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09019224
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Filing Dt:
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02/05/1998
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Title:
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CURRENT INJECTED RAMP WITH REDUCED RECOVERY TIME BACKGROUND OF THE INVENTION
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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09019521
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Filing Dt:
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02/05/1998
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Title:
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CHARGE BALANCED RAMP WITH IMPROVED SIGNAL LINEARITY
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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09019526
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Filing Dt:
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02/05/1998
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Title:
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TIMER WITH DYNAMIC RESET THRESHOLD
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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09063528
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Filing Dt:
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04/21/1998
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Title:
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DIFFERENTIAL COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) PUSH-PULL BUFFER
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09133287
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Filing Dt:
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08/12/1998
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Title:
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MEMORY INTERFACE UNIT, SHARED MEMORY SWITCH SYSTEM AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09168027
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Filing Dt:
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10/07/1998
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Title:
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IMPEDANCE MATCHED CMOS TRANSIMPEDANCE AMPLIFIER FOR HIGH-SPEED FIBER OPTIC COMMUNICATIONS
|
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|
|
Patent #:
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|
Issue Dt:
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07/31/2001
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Application #:
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09196830
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Filing Dt:
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11/20/1998
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Title:
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SINGLE INDUCTOR FULLY INTEGRATED DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR WITH AUTOMATIC AMPLITUDE ADJUSTMENT AND ON-CHIP VARACTOR
|
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|
|
|
Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09196831
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Filing Dt:
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11/20/1998
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Title:
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RADIO FREQUENCY VARIABLE GAIN AMPLIFIER FABRICATED IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TECHNOLOGY
|
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09197117
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Filing Dt:
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11/20/1998
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Title:
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RADIO FREQUENCY LOW NOISE AMPLIFIER FABRICATED IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TECHNOLOGY
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09221419
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Filing Dt:
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12/28/1998
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|
Title:
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MULTIPLEXER WITH SHORT PROPAGATION DELAY AND LOW POWER CONSUMPTION
|
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|
|
|
Patent #:
|
|
Issue Dt:
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01/28/2003
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Application #:
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09243583
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Filing Dt:
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02/03/1999
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|
Title:
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METHODS AND SYSTEMS FOR CONTROL AND CALIBRATION OF VCSEL-BASED OPTICAL TRANSCEIVERS
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|
|
|
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09243585
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Filing Dt:
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02/03/1999
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|
Title:
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HIGH-SPEED CMOS DRIVER FOR VERTICAL-CAVITY SURFACE-EMITTING LASERS
|
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|
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09253621
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Filing Dt:
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02/19/1999
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|
Title:
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OUTPUT BUFFER WITH PROGRAMMABLE VOLTAGE SWING
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|
|
|
Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09282883
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Filing Dt:
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03/31/1999
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Title:
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EMITTER FOLLOWER OUTPUT WITH PROGRAMMABLE CURRENT
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Patent #:
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|
Issue Dt:
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01/02/2001
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Application #:
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09303726
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Filing Dt:
|
05/03/1999
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Title:
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COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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12/10/2002
|
Application #:
|
09305248
|
Filing Dt:
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05/04/1999
|
|
Title:
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RECONFIGURABLE FRAME COUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09334170
|
Filing Dt:
|
06/15/1999
|
|
Title:
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SONET B2 PARITY BYTE CALCULATION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09340344
|
Filing Dt:
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06/25/1999
|
|
Title:
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SELF-ALIGNED NON-SELECTIVE THIN-EPI-BASE SILICON GERMANIUM (SIGE) HETEROJUNCTION BIPOLAR TRANSISTOR BICMOS PROCESS USING SILICON DIOXIDE ETCHBACK
|
|
|
|
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Patent #:
|
|
Issue Dt:
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04/24/2001
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Application #:
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09404640
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Filing Dt:
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09/23/1999
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|
Title:
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VOLTAGE/CURRENT REFERENCE WITH DIGITALLY PROGRAMMABLE TEMPERATURE COEFFICIENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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03/20/2001
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Application #:
|
09415271
|
Filing Dt:
|
10/07/1999
|
|
Title:
|
MEMORIES, SYSTEM USING MEMORIES, AND METHODS FOR ACCESSING MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09421957
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
BIPOLAR DEVICE WITH SILICON GERMANIUM (SIGE) BASE REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09478593
|
Filing Dt:
|
01/06/2000
|
|
Title:
|
IMPEDANCE MATCHED CMOS TRANSIMPEDANCE AMPLIFIER FOR HIGH-SPEED FIBER OPTIC COMMUNICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09516993
|
Filing Dt:
|
03/01/2000
|
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH THREE-DIMENSIONAL BASE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09527163
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
GIGABIT ETHERNET PERFORMANCE MONITORING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
09527343
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
TRANSPOSABLE FRAME SYNCHRONIZATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
09527348
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
MULTI-PORT DATA ARBITRATION CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
09527349
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
PROTOCOL INDEPENDENT PERFORMANCE MONITOR WITH SELECTABLE FEC ENCODING AND DECODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
09528021
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
PROGRAMMABLE SYNCHRONIZATION STRUCTURE WITH AUXILIARY DATA LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09542370
|
Filing Dt:
|
04/04/2000
|
|
Title:
|
SELECTIVE FLIP CHIP UNDERFILL PROCESSING FOR HIGH SPEED SIGNAL ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09636009
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
OUTPUT CONDUCTANCE CORRECTION CIRCUIT FOR HIGH COMPLIANCE SHORT-CHANNEL MOS SWITCHED CURRENT MIRROR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09656117
|
Filing Dt:
|
09/06/2000
|
|
Title:
|
SELF-ALIGNED NON-SELECTIVE THIN-EPI-BASE SILICON GERMANIUM (SIGE) HETEROJUNCTION BIPOLAR TRANSISTOR BICMOS PROCESS USING SILICON DIOXIDE ETCHBACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09675639
|
Filing Dt:
|
09/29/2000
|
|
Title:
|
MICROWAVE TO MILLIMETER WAVE FREQUENCY SUBSTRATE INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09708761
|
Filing Dt:
|
11/08/2000
|
|
Title:
|
TEMPERATURE STABLE CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
09746488
|
Filing Dt:
|
12/22/2000
|
|
Title:
|
SYSTEM AND METHOD FOR DIAGNOSING ERRORS IN MULTIDIMENSIONAL DIGITAL FRAME STRUCTURE COMMUNICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
09829214
|
Filing Dt:
|
04/09/2001
|
|
Title:
|
SYSTEM AND METHOD FOR SWITCH TIMING SYNCHRONIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09832779
|
Filing Dt:
|
04/11/2001
|
|
Title:
|
SYSTEM AND METHOD FOR SOLDER BALL REWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
09832784
|
Filing Dt:
|
04/11/2001
|
|
Title:
|
SYSTEM AND METHOD FOR SYSTOLIC ARRAY SORTING OF INFORMATION SEGMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
09836777
|
Filing Dt:
|
04/17/2001
|
|
Title:
|
TIME SLOT INTERCHANGING OF TIME SLOTS FROM MULTIPLE SONET SIGNALS WITHOUT FIRST PASSING THE SIGNALS THROUGH POINTER PROCESSORS TO SYNCHRONIZE THEM TO A COMMON CLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09871473
|
Filing Dt:
|
05/31/2001
|
|
Title:
|
INTEGRATED CIRCUIT TEMPLATE CELL SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09878736
|
Filing Dt:
|
06/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
High-speed CMOS driver for vertical-cavity surface-emitting lasers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
09919273
|
Filing Dt:
|
07/27/2001
|
|
Title:
|
PACKAGE SUBSTRATE INTERCONNECT LAYOUT FOR PROVIDING BANDPASS/LOWPASS FILTERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09941245
|
Filing Dt:
|
08/27/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2002
| | | | |
|
Title:
|
SINGLE INTERCONNECT, MULTI-BIT INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09957007
|
Filing Dt:
|
09/17/2001
|
|
Title:
|
FLIP-CHIP TRANSITION INTERFACE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09957115
|
Filing Dt:
|
09/17/2001
|
|
Title:
|
METHOD FOR DETERMINING A LAYOUT FOR A FLIP-CHIP TRANSITION INTERFACE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09957439
|
Filing Dt:
|
09/17/2001
|
|
Title:
|
FLIP-CHIP TRANSITION INTERFACE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
09965971
|
Filing Dt:
|
09/27/2001
|
|
Title:
|
METHODS AND APPARATUS FOR GENERATING A SUPPLY-INDEPENDENT AND TEMPERATURE-STABLE BIAS CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09966013
|
Filing Dt:
|
09/27/2001
|
|
Title:
|
METHODS AND APPARATUS FOR REDUCING THE CROWBAR CURRENT IN A DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10022673
|
Filing Dt:
|
12/17/2001
|
|
Title:
|
SYSTEM AND METHOD FOR SIMULTANEOUS DEFICIT ROUND ROBIN PRIORITIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10029581
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
SYSTEM AND METHOD FOR GRANTING ARBITRATED BIDS IN THE SWITCHING OF INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10034455
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
EMBEDDED FREQUENCY COUNTER WITH FLEXIBLE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10035835
|
Filing Dt:
|
12/24/2001
|
|
Title:
|
SYSTEM AND METHOD FOR HIERARCHICAL SWITCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10037959
|
Filing Dt:
|
12/21/2001
|
|
Title:
|
SYSTEM AND METHOD FOR GENERATING FORWARD ERROR CORRECTION BASED ALARMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
10075700
|
Filing Dt:
|
02/14/2002
|
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) FABRICATION USING A SELECTIVELY DEPOSITED SILICON GERMANIUM (SIGE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10094247
|
Filing Dt:
|
03/08/2002
|
|
Title:
|
SYSTEM AND METHOD FOR COMMUNICATING FAULT TYPE AND FAULT LOCATION MESSAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10094259
|
Filing Dt:
|
03/08/2002
|
|
Title:
|
SYSTEM AND METHOD FOR THE TRANSPORT OF BACKWARDS INFORMATION BETWEEN SIMPLEX DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10107662
|
Filing Dt:
|
03/26/2002
|
|
Title:
|
HIGH FREQUENCY SIGNAL TRANSMISSION FROM THE SURFACE OF A CIRCUIT SUBSTRATE TO A FLEXIBLE INTERCONNECT CABLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10107667
|
Filing Dt:
|
03/26/2002
|
|
Title:
|
FLEXIBLE INTERCONNECT CABLE WITH HIGH FREQUENCY ELECTRICAL TRANSMISSION LINE
|
|
|
|
|
Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10116177
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Filing Dt:
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04/03/2002
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Title:
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FAULT-TOLERANT DIGITAL COMMUNICATIONS CHANNEL HAVING SYNCHRONIZED UNIDIRECTIONAL LINKS
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Patent #:
|
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Issue Dt:
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06/01/2004
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Application #:
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10120576
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Filing Dt:
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04/09/2002
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Title:
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GLOBAL CLOCK TREE DE-SKEW
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10120599
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Filing Dt:
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04/09/2002
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Title:
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DIGITAL DELAY LOCK LOOP FOR SETUP AND HOLD TIME ENHANCEMENT
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10128610
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Filing Dt:
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04/22/2002
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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MODULAR MACRO CELL LAYOUT METHOD
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10138662
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Filing Dt:
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05/03/2002
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Title:
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ELECTRONIC DEVICE PACKAGE WITH HIGH SPEED SIGNAL INTERCONNECT BETWEEN DIE PAD AND EXTERNAL SUBSTRATE PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
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Application #:
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10145496
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Filing Dt:
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05/14/2002
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Title:
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FANNED OUT INTERCONNECT VIA STRUCTURE FOR ELECTRONIC PACKAGE SUBSTRATES
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|
|
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Patent #:
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Issue Dt:
|
08/10/2004
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Application #:
|
10154053
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Filing Dt:
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05/23/2002
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|
Title:
|
SYSTEM AND METHOD FOR INTERFACING A COAXIAL CONNECTOR TO A COPLANAR WAVEGUIDE SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
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Application #:
|
10170995
|
Filing Dt:
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06/13/2002
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Title:
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OPTICAL TRANSPORT NETWORK FRAME STRUCTURE WITH DYNAMICALLY ALLOCABLE IN-BAND DATA CHANNEL AND FORWARD ERROR CORRECTION BYTE CAPACITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
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Application #:
|
10171297
|
Filing Dt:
|
06/13/2002
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|
Title:
|
OPTICAL TRANSPORT NETWORK FRAME STRUCTURE WITH IN-BAND DATA CHANNEL AND FORWARD ERROR CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
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Application #:
|
10202322
|
Filing Dt:
|
07/23/2002
|
|
Title:
|
ELECTRONIC PACKAGE WITH OFFSET REFERENCE PLANE CUTOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10217209
|
Filing Dt:
|
08/12/2002
|
|
Title:
|
SYSTEM AND METHOD FOR MEASURING AMPLIFIER GAIN IN A DIGITAL NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
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Application #:
|
10218400
|
Filing Dt:
|
08/13/2002
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|
Title:
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HIGH PERFORMANCE DIFFERENTIAL AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
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Application #:
|
10224894
|
Filing Dt:
|
08/21/2002
|
|
Title:
|
SYSTEM AND METHOD FOR TESTING HIGH PIN COUNT ELECTRONIC DEVICES USING A TEST BOARD WITH LIMITED TEST CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
10238245
|
Filing Dt:
|
09/09/2002
|
|
Title:
|
TEMPERATURE STABLE CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
10254120
|
Filing Dt:
|
09/24/2002
|
|
Title:
|
ELECTRONIC PACKAGE SUBSTRATE WITH AN UPPER DIELECTRIC LAYER COVERING HIGH SPEED SIGNAL TRACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10254251
|
Filing Dt:
|
09/25/2002
|
|
Title:
|
POWER EFFICIENT EMITTER-COUPLED LOGIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10277290
|
Filing Dt:
|
10/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
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|
Title:
|
DEVICE FOR COUPLING DRIVE CIRCUITRY TO ELECTROABSORPTION MODULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10280978
|
Filing Dt:
|
10/24/2002
|
|
Title:
|
INTEGRATED CIRCUIT TEMPLATE CELL SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10290659
|
Filing Dt:
|
11/08/2002
|
|
Title:
|
METHOD AND APPARATUS FOR MAXIMIZING AN AMPLITUDE OF AN OUTPUT SIGNAL OF A DIFFERENTIAL MULTIPLEXER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10295065
|
Filing Dt:
|
11/15/2002
|
|
Title:
|
METHOD FOR MEASURING THE FREQUENCY RESPONSE OF A TRANSIMPEDANCE AMPLIFIER PACKAGED WITH AN INTEGRATED LIMITER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10304310
|
Filing Dt:
|
11/25/2002
|
|
Title:
|
RESET FEATURE FOR A LOW VOLTAGE DIFFERENTIAL LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10309522
|
Filing Dt:
|
12/03/2002
|
|
Title:
|
STACKABLE TEST APPARATUS FOR PROTECTING INTEGRATED CIRCUIT PACKAGES DURING TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10356167
|
Filing Dt:
|
01/31/2003
|
|
Title:
|
SIGNAL ROUTING IN A NODE OF A 1:N AUTOMATIC PROTECTION SWITCHING NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10373139
|
Filing Dt:
|
02/24/2003
|
|
Title:
|
SYSTEM AND METHOD FOR TOLERATING DATA LINK FAULTS IN A PACKET COMMUNICATIONS SWITCH FABRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10378403
|
Filing Dt:
|
03/03/2003
|
|
Title:
|
SYSTEM AND METHOD FOR COMMUNICATING SWITCH FABRIC CONTROL INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10378480
|
Filing Dt:
|
03/03/2003
|
|
Title:
|
SYSTEM AND METHOD FOR TOLERATING DATA LINK FAULTS IN COMMUNICATIONS WITH A SWITCH FABRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10378502
|
Filing Dt:
|
03/03/2003
|
|
Title:
|
MINIMUM LATENCY CUT-THROUGH SWITCH FABRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10378521
|
Filing Dt:
|
03/03/2003
|
|
Title:
|
SYSTEM AND METHOD FOR TOLERATING CONTROL LINK FAULTS IN A PACKET COMMUNICATIONS SWITCH FABRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10394843
|
Filing Dt:
|
03/21/2003
|
|
Title:
|
DUAL FUNCTION CLOCK SIGNAL SUITABLE FOR HOST CONTROL OF SYNCHRONOUS AND ASYNCHRONOUS TARGET DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10394845
|
Filing Dt:
|
03/21/2003
|
|
Title:
|
AMPLIFIER WITH DIGITAL DC OFFSET CANCELLATION FEATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10395367
|
Filing Dt:
|
03/24/2003
|
|
Title:
|
SYSTEM AND METHOD FOR SYNCHRONIZING SWITCH FABRIC BACKPLANE LINK MANAGEMENT CREDIT COUNTERS
|
|
