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Patent #:
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Issue Dt:
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08/28/1990
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Application #:
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06827269
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Filing Dt:
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02/06/1986
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Title:
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CUP CHIP HAVING CACHE TAG COMPARATOR AND ADDRESS TRANSLATION UNIT ON CHIP AND CONNECTED TO OFF-CHIP CACHE AND MAIN MEMORIES
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Patent #:
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Issue Dt:
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11/07/1989
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Application #:
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07161543
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Filing Dt:
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02/29/1988
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Title:
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METHOD AND APPARATUS FOR PRECISE FLOATING POINT EXCEPTIONS
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Patent #:
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Issue Dt:
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06/25/1991
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Application #:
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07255791
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Filing Dt:
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10/11/1988
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Title:
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PROCESSOR CONTROLLED INTERFACE WITH INSTRUCTION STREAMING
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Patent #:
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Issue Dt:
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09/25/1990
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Application #:
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07277406
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Filing Dt:
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11/28/1988
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Title:
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DUAL BYTE ORDER COMPUTER ARCHITECTURE A FUNCTIONAL UNIT FOR HANDLING DATA SETS WITH DIFFERENT BYTE ORDERS
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Patent #:
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Issue Dt:
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08/17/1993
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Application #:
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07366344
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Filing Dt:
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06/14/1989
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Title:
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TRANSLATION LOOKASIDE BUFFER SHUTDOWN SCHEME
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Patent #:
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Issue Dt:
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07/06/1993
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Application #:
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07444594
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Filing Dt:
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12/01/1989
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Title:
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TWO-LEVEL TRANSLATION LOOK-ASIDE BUFFER USING PARTIAL ADDRESSES FOR ENHANCED SPEED
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Patent #:
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Issue Dt:
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01/12/1993
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Application #:
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07444633
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Filing Dt:
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12/01/1989
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Title:
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SLOT DETERMINATION MECHANISM USING PULSE COUNTING
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Patent #:
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Issue Dt:
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05/05/1992
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Application #:
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07444639
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Filing Dt:
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12/01/1989
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Title:
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INTERRUPT REPORTING FOR SINGLE-BIT MEMORY ERRORS
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Patent #:
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Issue Dt:
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10/08/1991
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Application #:
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07448715
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Filing Dt:
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12/11/1989
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Title:
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DIFFERENTIAL BUS WITH SPECIFIED DEFAULT VALUE
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Patent #:
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Issue Dt:
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05/12/1992
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Application #:
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07491114
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Filing Dt:
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03/09/1990
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Title:
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SYSTEM HAVING AN ADDRESS GENERATING UNIT AND A TAG COMPARATOR PACKAGED AS AN INTEGRATED CIRCUIT SEPERATE FROM CACHE TAG MEMORY AND CACHE DATA MEMORY
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Patent #:
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Issue Dt:
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02/08/1994
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Application #:
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07573926
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Filing Dt:
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08/28/1990
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Title:
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LOW-NOISE HIGH-SPEED OUTPUT BUFFER AND METH0D FOR CONTROLLING SAME
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Patent #:
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Issue Dt:
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11/16/1993
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Application #:
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07644705
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Filing Dt:
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01/23/1991
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Title:
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VARIABLE PAGE SIZE PER ENTRY TRANSLATION LOOK-ASIDE BUFFER
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Patent #:
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Issue Dt:
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03/31/1992
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Application #:
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07659526
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Filing Dt:
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02/22/1991
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Title:
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VARIABLE DELAY LINE PHASE-LOCKED LOOP CIRCUIT SYNCHRONIZATION SYSTEM
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Patent #:
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Issue Dt:
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03/22/1994
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Application #:
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07892918
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Filing Dt:
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06/03/1992
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Title:
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SENSE AMP FOR BIT LINE SENSING AND DATA LATCHING
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Patent #:
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Issue Dt:
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07/05/1994
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Application #:
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07892919
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Filing Dt:
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06/03/1992
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Title:
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REDUNDANCY SELECTION APPARATUS AND METHOD FOR AN ARRAY
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Patent #:
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Issue Dt:
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04/05/1994
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Application #:
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07893156
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Filing Dt:
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06/03/1992
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Title:
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REDUNDANT ELEMENT SUBSTITUTION APPARATUS
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Patent #:
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Issue Dt:
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04/18/1995
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Application #:
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07901910
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Filing Dt:
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06/19/1992
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Title:
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SYSTEM AND METHOD FOR BOOTING COMPUTER FOR OPERATION IN EITHER OF TWO BYTE-ORDER MODES
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Patent #:
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Issue Dt:
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02/13/1996
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Application #:
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07918819
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Filing Dt:
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07/22/1992
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Title:
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APPARATUS FOR DETECTING ANY SINGLE BIT ERROR, DETECTING ANY TWO BIT ERROR, AND DETECTING ANY THREE OR FOUR BIT ERROR IN A GROUP OF FOUR BITS FOR A 25- OR 64- BIT DATA WORD
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Patent #:
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Issue Dt:
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05/31/1994
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Application #:
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07933467
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Filing Dt:
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08/21/1992
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Title:
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CLOCK DISTRIBUTION SYSTEM FOR AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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11/12/1996
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Application #:
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07951471
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Filing Dt:
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09/25/1992
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Title:
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TLB WITH TWO PHYSICAL PAGES PER VIRTUAL TAG
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Patent #:
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Issue Dt:
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05/03/1994
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Application #:
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07956867
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Filing Dt:
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10/01/1992
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Title:
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BINARY SHIFTER
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Patent #:
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Issue Dt:
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06/28/1994
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Application #:
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08019541
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Filing Dt:
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02/18/1993
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Title:
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TRANSLATION LOOKASIDE BUFFER SHUTDOWN SCHEME
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Patent #:
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Issue Dt:
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04/26/1994
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Application #:
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08059715
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Filing Dt:
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05/10/1993
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Title:
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CACHE MEMORY SYSTEM EMPLOYING VIRTUAL ADDRESS PRIMARY INSTRUCTION AND DATA CACHES AND PHYSICAL ADDRESS SECONDARY CACHE
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Patent #:
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Issue Dt:
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09/12/1995
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Application #:
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08063183
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Filing Dt:
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05/17/1993
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Title:
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UNIFIED FLOATING POINT AND INTEGER DATAPATH FOR A RISC PROCESSOR
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Patent #:
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Issue Dt:
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03/14/1995
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Application #:
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08127105
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Filing Dt:
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09/27/1993
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Title:
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SYSTEM FOR OBTAINING CORRECT BYTE ADDRESSES BY XOR-ING 2 LSB BITS OF BYTE ADDRESS WITH BINARY 3 TO FACILITATE COMPATIBILITY BETWEEN COMPUTER ARCHITECTURE HAVING DIFFERENT MEMORY ORDERS
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Patent #:
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Issue Dt:
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07/16/1996
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Application #:
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08166969
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Filing Dt:
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12/15/1993
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Title:
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DEBUG MODE FOR A SUPERSCALAR RISC PROCESSOR
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Patent #:
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Issue Dt:
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11/05/1996
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Application #:
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08167005
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Filing Dt:
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12/15/1993
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Title:
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SYSTEM AND METHOD FOR CONTROLLING SPLIT- LEVEL CACHES IN A MULI- PROCESSOR SYSTEM INCLUDING DATA LOSS AND DEADLOCK PREVENTION SCHEMES
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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08167006
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Filing Dt:
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12/15/1993
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Title:
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MECHANISM AND METHOD FOR INTEGER DIVIDE INVOLVING PRE-ALIGNMENT OF THE DIVISOR RELATIVE TO THE DIVIDEND
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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08168744
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Filing Dt:
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12/15/1993
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Title:
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APPARATUS FOR PROCESSING INSTRUCTIONS IN A COMPUTING SYSTEM
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Patent #:
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Issue Dt:
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06/11/1996
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Application #:
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08168822
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Filing Dt:
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12/15/1993
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Title:
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VARIABLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER
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Patent #:
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Issue Dt:
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04/23/1996
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Application #:
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08168832
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Filing Dt:
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12/15/1993
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Title:
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MEMORY SYSTEM INCLUDING LOCAL AND GLOBAL CACHES FOR STORING FLOATING POINT AND INTEGER DATA
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Patent #:
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Issue Dt:
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07/30/1996
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Application #:
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08172684
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Filing Dt:
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12/22/1993
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Title:
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CACHE MEMORY SYSTEM EMPLOYING VIRTUAL ADDRESS PRIMARY INSTRUCTION AND DATA CACHES AND PHYSICAL ADDRESS SECONDARY CACHE
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Patent #:
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Issue Dt:
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12/26/1995
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Application #:
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08212377
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Filing Dt:
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03/11/1994
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Title:
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HYBRID CACHE HAVING PHYSICAL-CACHE AND VIRTUAL-CACHE CHARACTERISTICS AND METHOD FOR ACCESSING SAME
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Patent #:
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Issue Dt:
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05/30/1995
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Application #:
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08223388
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Filing Dt:
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04/05/1994
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Title:
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BACKWARD-COMPATIBLE COMPUTER ARCHITECTURE WITH EXTENDED WORD SIZE AND ADDRESS SPACE
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Patent #:
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Issue Dt:
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04/02/1996
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Application #:
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08245200
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Filing Dt:
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05/17/1994
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Title:
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COMPACT DUAL FUNCTION ADDER
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08245983
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Filing Dt:
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05/17/1994
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Title:
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PRECISE TRANSLATION LOOKASIDE BUFFER ERROR DETECTION AND SHUTDOWN CIRCUIT
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Patent #:
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Issue Dt:
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09/10/1996
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Application #:
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08324861
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Filing Dt:
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10/18/1994
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Title:
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RESCHEDULING CONFLICTING ISSUED INSTRUCTIONS BY DELAYING ONE CONFLICTING INSTRUCTION INTO THE SAME PIPELINE STAGE AS A THIRD NON-CONFLICTING INSTRUCTION
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Patent #:
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Issue Dt:
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06/04/1996
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Application #:
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08378844
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Filing Dt:
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01/26/1995
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Title:
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SYSTEM FOR BOOTING COMPUTER FOR OPERATION IN EITHER ONE OF TWO BYTE-ORDER MODES
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Patent #:
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Issue Dt:
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11/05/1996
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Application #:
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08379710
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Filing Dt:
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01/27/1995
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Title:
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SYSTEM AND METHOD FOR OBTAINING CORRECT BYTE ADDRESSES BY USING LOGICAL OPERATIONS ON 2 LEAST SIGNIFICANT BITS OF BYTE ADDRESS TO FACILITATE COMPATIBILITY BETWEEN COMPUTER ARCHITECTURES HAVING DIFFERENT MEMORY ORDERS
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Patent #:
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Issue Dt:
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10/22/1996
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Application #:
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08391946
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Filing Dt:
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02/21/1995
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Title:
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BACKWARD-COMPATIBLE COMPUTER ARCHITECTURE WITH EXTENDED WORD SIZE AND ADDRESS SPACE
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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08404625
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Filing Dt:
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03/14/1995
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Title:
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ADDRESS QUEUE
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Patent #:
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Issue Dt:
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12/09/1997
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Application #:
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08405622
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Filing Dt:
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03/15/1995
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Title:
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METHOD AND APPARATUS FOR REDUCING DELAYS FOLLOWING THE EXECUTION OF A BRANCH INSTRUCTION PIPELINE
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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08410524
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Filing Dt:
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03/24/1995
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Title:
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CONSISTENTLY SPECIFYING WAY DESTINATIONS THROUGH PREFETCHING HINTS
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Patent #:
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Issue Dt:
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12/31/1996
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Application #:
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08449588
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Filing Dt:
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05/24/1995
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Title:
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METHOD AND APPARATUS FOR RESTARTING PIPELINE PROCESSING
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08484313
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Filing Dt:
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06/07/1995
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Title:
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SOFTWARE INVALIDATION IN A MULTIPLE LEVEL MULTIPLE CACHE SYSTEM
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Patent #:
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Issue Dt:
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04/14/1998
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Application #:
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08487240
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Filing Dt:
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06/13/1995
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Title:
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CONFLICT RESOLUTION IN INTERLEAVED MEMORY SYSTEMS WITH MULTIPLE PARALLEL ACCESSES
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Patent #:
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Issue Dt:
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10/22/1996
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Application #:
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08491491
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Filing Dt:
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06/16/1995
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Title:
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RISC PROCESSOR HAVING IMPROVED INSTRUCTION FETCHING CAPABILITY AND UTILIZING ADDRESS BIT PREDECODING FOR A SEGMENTED CACHE MEMORY
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Patent #:
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Issue Dt:
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09/23/1997
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Application #:
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08561914
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Filing Dt:
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11/22/1995
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Title:
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LOW-POWER, COMPACT DIGITAL LOGIC TOPOLOGY THAT FACILITATES LARGE FAN-IN AND HIGH-SPEED CIRCUIT PERFORMANCE
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08686363
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Filing Dt:
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07/24/1996
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Title:
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SYSTEM AND METHOD FOR FETCHING MULTIPLE GROUPS OF INSTRUCTIONS FROM AN INTSTRUCTION CACHE IN A RISC PROCESSOR SYSTEM FOR EXECUTION DURING SEPARATE CYCLES
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Patent #:
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Issue Dt:
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05/20/1997
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Application #:
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08696788
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Filing Dt:
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08/14/1996
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Title:
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METHOD FOR PREVENTING MULTI-LEVEL CACHE SYSTEM DEADLOCK IN A MULTI- PROCESSOR SYSTEM
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Patent #:
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Issue Dt:
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03/31/1998
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Application #:
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08715246
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Filing Dt:
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09/19/1996
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Title:
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PROCESSOR CHIP HAVING ON-CHIP CIRCUITRY FOR GENERATING A PROGRAMMABLE EXTERNAL CLOCK SIGNAL AND FOR CONTROLLING DATA PATTERNS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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08772233
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Filing Dt:
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12/23/1996
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Title:
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TRANSLATION LOOKASIDE BUFFER WITH VIRTUAL ADDRESS CONFLICT PREVENTION
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08781851
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Filing Dt:
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01/10/1997
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Title:
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INVALIDATING INSTRUCTIONS IN FETCHED INSTRUCTION BLOCKS UPON PREDICTED TWO-STEP BRANCH OPERATIONS WITH SECOND OPERATION RELATIVE TARGET ADDRESS
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Patent #:
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Issue Dt:
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05/26/1998
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Application #:
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08796142
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Filing Dt:
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02/07/1997
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Title:
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PIPELINE PROCESSOR WITH ENHANCED METHOD AND APPARATUS FOR RESTORING REGISTER-RENAMING INFORMATION IN THE EVENT OF A BRANCH MISPREDICTION
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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08813500
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Filing Dt:
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03/07/1997
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Title:
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CACHE MEMORY WITH DUAL-WAY ARRAYS AND MULTIPLEXED PARALLEL OUTPUT
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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08935369
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Filing Dt:
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09/22/1997
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Title:
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INSTRUCTION PREDICTION BASED ON FILTERING
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Patent #:
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Issue Dt:
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01/26/1999
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Application #:
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08947648
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Filing Dt:
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10/09/1997
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Title:
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METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08947649
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Filing Dt:
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10/09/1997
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Title:
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ALIGNMENT AND ORDERING OF VECTOR ELEMENTS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSING
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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08982244
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Filing Dt:
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12/01/1997
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Title:
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PREFETCHING HINTS
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09036684
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Filing Dt:
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03/09/1998
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Title:
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EXTERNAL CLOCK GENERATOR FOR A MICROPROCESSOR
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09216017
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Filing Dt:
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12/16/1998
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Publication #:
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Pub Dt:
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05/23/2002
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Title:
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PRIORITIZED INSTRUCTION SCHEDULING FOR MULTI-STREAMING PROCESSORS
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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09223046
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Filing Dt:
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12/30/1998
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Publication #:
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Pub Dt:
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05/23/2002
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Title:
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METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09240012
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Filing Dt:
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01/27/1999
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Title:
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REGISTER TRANSFER UNIT FOR ELECTRONIC PROCESSOR
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09263798
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Filing Dt:
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03/05/1999
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Title:
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ALIGNMENT AND ORDERING OF VECTOR ELEMENTS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSING
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09273810
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Filing Dt:
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03/22/1999
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Title:
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INTERSTREAM CONTROL AND COMMUNICATIONS FOR MULTI-STREAMING DIGITAL PROCESSORS
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09302246
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Filing Dt:
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04/29/1999
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Title:
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REGISTER FILE ACCESS
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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09312302
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Filing Dt:
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05/14/1999
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Title:
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INTERRUPT AND EXCEPTION HANDLING FOR MULTI-STREAMING DIGITAL PROCESSORS
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09318551
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Filing Dt:
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05/27/1999
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Title:
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LOW LATENCY SYSTEM BUS INTERFACE FOR MULTI-MASTER PROCESSING ENVIRONMENTS
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09363635
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Filing Dt:
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07/30/1999
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Title:
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BRANCH PREDICTION ENTRY WITH TARGET LINE INDEX CALCULATED USING RELATIVE POSITION OF SECOND OPERATION OF TWO STEP BRANCH OPERATION IN A LINE OF INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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09363637
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Filing Dt:
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07/30/1999
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Title:
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SYSTEM AND METHOD FOR IMPROVING THE ACCURACY OF RECIPROCAL SQUARE ROOT OPERATIONS PERFORMED BY A FLOATING-POINT UNIT
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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09363638
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Filing Dt:
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07/30/1999
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Title:
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METHOD AND APPARATUS FOR PREDICTING FLOATING-POINT EXCEPTIONS
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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09364512
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Filing Dt:
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07/30/1999
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Title:
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PROCESSOR WITH IMPROVED ACCURACY FOR MULTIPLY-ADD OPERATIONS
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09364514
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Filing Dt:
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07/30/1999
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Title:
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FLOATING-POINT PROCESSOR WITH IMPROVED INTERMEDIATE RESULT HANDLING
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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09364786
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Filing Dt:
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07/30/1999
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Title:
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PROCESSOR HAVING A COMPARE EXTENSION OF AN INSTRUCTION SET ARCHITECTURE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09364787
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Filing Dt:
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07/30/1999
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Title:
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PROCESSOR HAVING AN ARITHMETIC EXTENSION OF AN INSTRUCTION SET ARCHITECTURE
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09364789
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Filing Dt:
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07/30/1999
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Title:
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PROCESSOR HAVING A CONDITIONAL BRANCH EXTENSION OF AN INSTRUCTION SET ARCHITECTURE
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09373091
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Filing Dt:
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08/12/1999
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Title:
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SCALABLE ON-CHIP SYSTEM BUS
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09373092
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Filing Dt:
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08/12/1999
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Title:
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LOCKED READ/WRITE ON SEPARATE ADDRESS/DATA BUS USING WRITE BARRIER
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09373093
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Filing Dt:
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08/12/1999
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Title:
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DATA RELEASE TO REDUCE LATENCY IN ON-CHIP SYSTEM BUS
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09373094
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Filing Dt:
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08/12/1999
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Title:
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COHERENT DATA APPARATUS FOR AN ON-CHIP SPLIT TRANSACTION SYSTEM BUS
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09373095
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Filing Dt:
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08/12/1999
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Title:
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BURST-CONFIGURABLE DATA BUS
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09383401
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Filing Dt:
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08/26/1999
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Title:
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OUTPUT SYNCHRONIZATION-FREE, HIGH-FANIN DYNAMIC NOR GATE
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09494488
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Filing Dt:
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01/31/2000
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Title:
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SCRATCHPAD RAM MEMORY ACCESSIBLE IN PARALLEL TO A PRELIMARY CACHE
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09517272
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Filing Dt:
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03/02/2000
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Title:
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METHOD AND APPARATUS FOR TRACKING AND UPDATE OF LRU ALGORITHM USING VECTORS
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09544352
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Filing Dt:
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04/06/2000
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Title:
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Instruction prediction based on filtering
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09577238
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Filing Dt:
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05/23/2000
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Title:
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FLOATING-POINT PROCESSOR WITH OPERATING MODE HAVING IMPROVED ACCURACY AND HIGH PERFORMANCE
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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09586115
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Filing Dt:
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06/02/2000
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Title:
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WIRE-SPEED MULTI-DIMENSIONAL PACKET CLASSIFIER
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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09591510
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Filing Dt:
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06/12/2000
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Title:
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Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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09592106
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Filing Dt:
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06/12/2000
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING ATOMICITY OF MEMORY OPERATIONS IN DYNAMIC MULTI-STREAMING PROCESSORS
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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09595776
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Filing Dt:
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06/16/2000
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Title:
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INSTRUCTION FETCHING SYSTEM IN A MULTITHREADED PROCESSOR UTILIZING CACHE MISS PREDICTIONS TO FETCH INSTRUCTIONS FROM MULTIPLE HARDWARE STREAMS
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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09602279
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Filing Dt:
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06/23/2000
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Title:
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BACKGROUND MEMORY MANAGER THAT DETERMINES IF DATA STRUCTURES FITS IN MEMORY WITH MEMORY STATE TRANSACTIONS MAP
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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09608750
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Filing Dt:
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06/30/2000
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Title:
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METHODS AND APPARATUS FOR MANAGING A BUFFER OF EVENTS IN THE BACKGROUND
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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09616385
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Filing Dt:
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07/14/2000
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Title:
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METHODS AND APPARATUS FOR IMPROVING FETCHING AND DISPATCH OF INSTRUCTIONS IN MULTITHREADED PROCESSORS
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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09637500
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Filing Dt:
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08/11/2000
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Title:
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HIGH PERFORMANCE RISC INSTRUCTION SET DIGITAL SIGNAL PROCESSOR HAVING CIRCULAR BUFFER AND LOOPING CONTROLS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09654064
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Filing Dt:
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09/01/2000
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Title:
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REGISTER SET EXTENSION FOR COMPRESSED INSTRUCTION SET
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|
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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09662832
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Filing Dt:
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09/15/2000
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Title:
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ALIGNMENT AND ORDERING OF VECTOR ELEMENTS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSING
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09665099
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Filing Dt:
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09/20/2000
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Title:
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SYSTEM FOR PREDICTION AND CONTROL OF POWER CONSUMPTION IN DIGITAL SYSTEM
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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09702112
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Filing Dt:
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10/30/2000
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Title:
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CHANGING INSTRUCTION SET ARCHITECTURE MODE BY COMPARISON OF CURRENT INSTRUCTION EXECUTION ADDRESS WITH BOUNDARY ADDRESS REGISTER VALUES
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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09706154
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Filing Dt:
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11/03/2000
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Title:
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FETCH AND DISPATCH DISASSOCIATION APPARATUS FOR MULTISTREMING PROCESSORS
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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09706157
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Filing Dt:
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11/03/2000
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Title:
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CLUSTERING STREAM AND/OR INSTRUCTION QUEUES FOR MULTI-STREAMING PROCESSORS
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