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Reel/Frame:022343/0351   Pages: 10
Recorded: 03/04/2009
Attorney Dkt #:TPL-0002
Conveyance: LICENSE (SEE DOCUMENT FOR DETAILS).
Total properties: 38
1
Patent #:
6809608
Issue Dt:
10/26/2004
Application #:
10094761
Filing Dt:
03/11/2002
Publication #:
US20030001698
Pub Dt:
01/02/2003
Title:
TRANSMISSION LINE STRUCTURE WITH AN AIR DIELECTRIC
2
Patent #:
6933610
Issue Dt:
08/23/2005
Application #:
10370422
Filing Dt:
02/19/2003
Publication #:
US20030205802
Pub Dt:
11/06/2003
Title:
METHOD OF BONDING A SEMICONDUCTOR DIE WITHOUT AN ESD CIRCUIT AND A SEPARATE ESD CIRCUIT TO AN EXTERNAL LEAD, AND A SEMICONDUCTOR DEVICE MADE THEREBY
3
Patent #:
7307293
Issue Dt:
12/11/2007
Application #:
10426930
Filing Dt:
04/29/2003
Publication #:
US20030222282
Pub Dt:
12/04/2003
Title:
DIRECT-CONNECT INTEGRATED CIRCUIT SIGNALING SYSTEM FOR BYPASSING INTRA-SUBSTRATE PRINTED CIRCUIT SIGNAL PATHS
4
Patent #:
6884120
Issue Dt:
04/26/2005
Application #:
10608255
Filing Dt:
06/27/2003
Title:
ARRAY CONNECTOR WITH DEFLECTABLE COUPLING STRUCTURE FOR MATING WITH OTHER COMPONENTS
5
Patent #:
6891272
Issue Dt:
05/10/2005
Application #:
10632730
Filing Dt:
07/31/2003
Title:
MULTI-PATH VIA INTERCONNECTION STRUCTURES AND METHODS FOR MANUFACTURING THE SAME
6
Patent #:
7014472
Issue Dt:
03/21/2006
Application #:
10756924
Filing Dt:
01/13/2004
Publication #:
US20050014395
Pub Dt:
01/20/2005
Title:
SYSTEM FOR MAKING HIGH-SPEED CONNECTIONS TO BOARD-MOUNTED MODULES
7
Patent #:
7308524
Issue Dt:
12/11/2007
Application #:
10757000
Filing Dt:
01/13/2004
Publication #:
US20040148482
Pub Dt:
07/29/2004
Title:
MEMORY CHAIN
8
Patent #:
7111108
Issue Dt:
09/19/2006
Application #:
10823499
Filing Dt:
04/12/2004
Publication #:
US20040236894
Pub Dt:
11/25/2004
Title:
MEMORY SYSTEM HAVING A MULTIPLEXED HIGH-SPEED CHANNEL
9
Patent #:
7701323
Issue Dt:
04/20/2010
Application #:
10857830
Filing Dt:
06/01/2004
Title:
LOW PROFILE DISCRETE ELECTRONIC COMPONENTS AND APPLICATIONS OF SAME
10
Patent #:
7061096
Issue Dt:
06/13/2006
Application #:
10947686
Filing Dt:
09/23/2004
Publication #:
US20050093127
Pub Dt:
05/05/2005
Title:
MULTI-SURFACE IC PACKAGING STRUCTURES AND METHODS FOR THEIR MANUFACTURE
11
Patent #:
7732904
Issue Dt:
06/08/2010
Application #:
10964578
Filing Dt:
10/12/2004
Publication #:
US20050093152
Pub Dt:
05/05/2005
Title:
MULTI-SURFACE CONTACT IC PACKAGING STRUCTURES AND ASSEMBLIES
12
Patent #:
7176580
Issue Dt:
02/13/2007
Application #:
10973172
Filing Dt:
10/25/2004
Title:
STRUCTURES AND METHODS FOR WIRE BONDING OVER ACTIVE, BRITTLE AND LOW K DIELECTRIC AREAS OF AN IC CHIP
13
Patent #:
7279783
Issue Dt:
10/09/2007
Application #:
10977355
Filing Dt:
10/29/2004
Title:
PARTITIONED INTEGRATED CIRCUIT PACKAGE WITH CENTRAL CLOCK DRIVER
14
Patent #:
7388279
Issue Dt:
06/17/2008
Application #:
10987187
Filing Dt:
11/12/2004
Publication #:
US20050133922
Pub Dt:
06/23/2005
Title:
TAPERED DIELECTRIC AND CONDUCTOR STRUCTURES AND APPLICATIONS THEREOF
15
Patent #:
7280372
Issue Dt:
10/09/2007
Application #:
10990280
Filing Dt:
11/15/2004
Publication #:
US20050103522
Pub Dt:
05/19/2005
Title:
STAIR STEP PRINTED CIRCUIT BOARD STRUCTURES FOR HIGH SPEED SIGNAL TRANSMISSIONS
16
Patent #:
7205613
Issue Dt:
04/17/2007
Application #:
11033354
Filing Dt:
01/07/2005
Publication #:
US20050146821
Pub Dt:
07/07/2005
Title:
INSULATING SUBSTRATE FOR IC PACKAGES HAVING INTEGRAL ESD PROTECTION
17
Patent #:
7652381
Issue Dt:
01/26/2010
Application #:
11055578
Filing Dt:
02/09/2005
Publication #:
US20050189640
Pub Dt:
09/01/2005
Title:
INTERCONNECT SYSTEM WITHOUT THROUGH-HOLES
18
Patent #:
7278855
Issue Dt:
10/09/2007
Application #:
11055579
Filing Dt:
02/09/2005
Publication #:
US20050239300
Pub Dt:
10/27/2005
Title:
HIGH SPEED, DIRECT PATH, STAIR-STEP, ELECTRONIC CONNECTORS WITH IMPROVED SIGNAL INTEGRITY CHARACTERISTICS AND METHODS FOR THEIR MANUFACTURE
19
Patent #:
7310239
Issue Dt:
12/18/2007
Application #:
11062112
Filing Dt:
02/18/2005
Title:
IC PACKAGING INTERPOSER HAVING CONTROLLED IMPEDANCE OR OPTICAL INTERCONNECTIONS AND AN INTEGRAL HEAT SPREADER
20
Patent #:
7347697
Issue Dt:
03/25/2008
Application #:
11092034
Filing Dt:
03/28/2005
Publication #:
US20050215089
Pub Dt:
09/29/2005
Title:
ACTIVE CONNECTOR
21
Patent #:
7192320
Issue Dt:
03/20/2007
Application #:
11093266
Filing Dt:
03/28/2005
Publication #:
US20050221680
Pub Dt:
10/06/2005
Title:
ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
22
Patent #:
7227759
Issue Dt:
06/05/2007
Application #:
11097450
Filing Dt:
04/01/2005
Publication #:
US20060034061
Pub Dt:
02/16/2006
Title:
SIGNAL-SEGREGATING CONNECTOR SYSTEM
23
Patent #:
7845986
Issue Dt:
12/07/2010
Application #:
11123863
Filing Dt:
05/06/2005
Publication #:
US20060035482
Pub Dt:
02/16/2006
Title:
TORSIONALLY-INDUCED CONTACT-FORCE CONDUCTORS FOR ELECTRICAL CONNECTOR SYSTEMS
24
Patent #:
7750446
Issue Dt:
07/06/2010
Application #:
11182484
Filing Dt:
07/14/2005
Publication #:
US20060091507
Pub Dt:
05/04/2006
Title:
IC PACKAGE STRUCTURES HAVING SEPARATE CIRCUIT INTERCONNECTION STRUCTURES AND ASSEMBLIES CONSTRUCTED THEREOF
25
Patent #:
7737545
Issue Dt:
06/15/2010
Application #:
11353564
Filing Dt:
02/13/2006
Publication #:
US20060157846
Pub Dt:
07/20/2006
Title:
MULTI-SURFACE IC PACKAGING STRUCTURES AND METHODS FOR THEIR MANUFACTURE
26
Patent #:
7466021
Issue Dt:
12/16/2008
Application #:
11381357
Filing Dt:
05/02/2006
Publication #:
US20060244150
Pub Dt:
11/02/2006
Title:
MEMORY PACKAGES HAVING STAIR STEP INTERCONNECTION LAYERS
27
Patent #:
7404746
Issue Dt:
07/29/2008
Application #:
11607143
Filing Dt:
12/01/2006
Publication #:
US20070178774
Pub Dt:
08/02/2007
Title:
ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
28
Patent #:
7613011
Issue Dt:
11/03/2009
Application #:
11748045
Filing Dt:
05/14/2007
Publication #:
US20070236901
Pub Dt:
10/11/2007
Title:
SIGNAL-SEGREGATING CONNECTOR SYSTEM
29
Patent #:
7651336
Issue Dt:
01/26/2010
Application #:
11868947
Filing Dt:
10/08/2007
Publication #:
US20090093173
Pub Dt:
04/09/2009
Title:
HIGH SPEED, DIRECT PATH, STAIR-STEP, ELECTRONIC CONNECTORS WITH IMPROVED SIGNAL INTEGRITY CHARACTERISTICS AND METHODS FOR THEIR MANUFACTURE
30
Patent #:
NONE
Issue Dt:
Application #:
11868963
Filing Dt:
10/09/2007
Publication #:
US20090091017
Pub Dt:
04/09/2009
Title:
Partitioned Integrated Circuit Package with Central Clock Driver
31
Patent #:
7989929
Issue Dt:
08/02/2011
Application #:
11930217
Filing Dt:
10/31/2007
Publication #:
US20090108416
Pub Dt:
04/30/2009
Title:
DIRECT-CONNECT SIGNALING SYSTEM
32
Patent #:
7966443
Issue Dt:
06/21/2011
Application #:
11933445
Filing Dt:
11/01/2007
Publication #:
US20090119464
Pub Dt:
05/07/2009
Title:
MEMORY SYSTEMS INCLUDING MEMORY DEVICES COUPLED TOGETHER IN A DAISY-CHAINED ARRANGEMENT
33
Patent #:
8338713
Issue Dt:
12/25/2012
Application #:
11939554
Filing Dt:
11/14/2007
Publication #:
US20090120668
Pub Dt:
05/14/2009
Title:
CABLED SIGNALING SYSTEM AND COMPONENTS THEREOF
34
Patent #:
7948093
Issue Dt:
05/24/2011
Application #:
11965705
Filing Dt:
12/27/2007
Publication #:
US20080211071
Pub Dt:
09/04/2008
Title:
MEMORY IC PACKAGE ASSEMBLY HAVING STAIR STEP METAL LAYER AND APERTURES
35
Patent #:
7651382
Issue Dt:
01/26/2010
Application #:
12127195
Filing Dt:
05/27/2008
Publication #:
US20080274654
Pub Dt:
11/06/2008
Title:
ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
36
Patent #:
7973391
Issue Dt:
07/05/2011
Application #:
12128620
Filing Dt:
05/29/2008
Publication #:
US20090027137
Pub Dt:
01/29/2009
Title:
TAPERED DIELECTRIC AND CONDUCTOR STRUCTURES AND APPLICATIONS THEREOF
37
Patent #:
NONE
Issue Dt:
Application #:
12335372
Filing Dt:
12/15/2008
Publication #:
US20090091019
Pub Dt:
04/09/2009
Title:
INTEGRATED CIRCUIT PACKAGES AND ELECTRICAL ASSEMBLIES HAVING STAIR STEP INTERCONNECTION LAYERS
38
Patent #:
8026600
Issue Dt:
09/27/2011
Application #:
12348273
Filing Dt:
01/02/2009
Publication #:
US20090167334
Pub Dt:
07/02/2009
Title:
CONTROLLED IMPEDANCE STRUCTURES FOR HIGH DENSITY INTERCONNECTIONS
Assignor
1
INTERCONNECT PORTFOLIO LLC
Exec Dt:
03/15/2008
Assignee
1
TECHNOLOGY PROPERTIES LIMITED LLC
20400 STEVENS CREEK BLVD.
FIFTH FLOOR
CUPERTINO, CALIFORNIA 95014
Correspondence name and address
MARK SALVATORE
20400 STEVENS CREEK BLVD.
FIFTH FLOOR
CUPERTINO, CA 95014

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