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Reel/Frame:	022793/0565			Pages:	12
		Recorded:	06/09/2009
Attorney Dkt #:	5888-00000/LJM
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 68

Patent #:	7218562	Issue Dt:	05/15/2007	Application #:	11173119	Filing Dt:	07/01/2005
Publication #:	US20070002650	Pub Dt:	01/04/2007
Title:	RECOVERING BIT LINES IN A MEMORY ARRAY AFTER STOPPED CLOCK OPERATION

Patent #:	7355905	Issue Dt:	04/08/2008	Application #:	11173565	Filing Dt:	07/01/2005
Publication #:	US20070002636	Pub Dt:	01/04/2007
Title:	INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE

Patent #:	7564226	Issue Dt:	07/21/2009	Application #:	11173582	Filing Dt:	07/01/2005
Publication #:	US20070001747	Pub Dt:	01/04/2007
Title:	RAPID SUPPLY VOLTAGE RAMP USING CHARGED CAPACITOR AND SWITCH

Patent #:	7276925	Issue Dt:	10/02/2007	Application #:	11173684	Filing Dt:	07/01/2005
Publication #:	US20070001697	Pub Dt:	01/04/2007
Title:	OPERATING AN INTEGRATED CIRCUIT AT A MINIMUM SUPPLY VOLTAGE

Patent #:	8015356	Issue Dt:	09/06/2011	Application #:	11173685	Filing Dt:	07/01/2005
Publication #:	US20070005891	Pub Dt:	01/04/2007
Title:	FAST HIT OVERRIDE

Patent #:	7500044	Issue Dt:	03/03/2009	Application #:	11176520	Filing Dt:	07/07/2005
Publication #:	US20070011368	Pub Dt:	01/11/2007
Title:	DIGITAL PHASE RELATIONSHIP LOCK LOOP

Patent #:	7376817	Issue Dt:	05/20/2008	Application #:	11200744	Filing Dt:	08/10/2005
Publication #:	US20070038846	Pub Dt:	02/15/2007
Title:	PARTIAL LOAD/STORE FORWARD PREDICTION

Patent #:	8117404	Issue Dt:	02/14/2012	Application #:	11200771	Filing Dt:	08/10/2005
Publication #:	US20070038847	Pub Dt:	02/15/2007
Title:	MISALIGNMENT PREDICTOR

Patent #:	7269682	Issue Dt:	09/11/2007	Application #:	11201573	Filing Dt:	08/11/2005
Publication #:	US20070038796	Pub Dt:	02/15/2007
Title:	SEGMENTED INTERCONNECT FOR CONNECTING MULTIPLE AGENTS IN A SYSTEM

Patent #:	7461190	Issue Dt:	12/02/2008	Application #:	11201581	Filing Dt:	08/11/2005
Publication #:	US20070038791	Pub Dt:	02/15/2007
Title:	NON-BLOCKING ADDRESS SWITCH WITH SHALLOW PER AGENT QUEUES

Patent #:	7187606	Issue Dt:	03/06/2007	Application #:	11208911	Filing Dt:	08/22/2005
Publication #:	US20070041250	Pub Dt:	02/22/2007
Title:	READ PORT CIRCUIT FOR REGISTER FILE

Patent #:	7277353	Issue Dt:	10/02/2007	Application #:	11208912	Filing Dt:	08/22/2005
Publication #:	US20070041262	Pub Dt:	02/22/2007
Title:	REGISTER FILE

Patent #:	NONE	Issue Dt:		Application #:	11211259	Filing Dt:	08/25/2005
Publication #:	US20070047572	Pub Dt:	03/01/2007
Title:	Explicit flow control in Gigabit/10 Gigabit Ethernet system

Patent #:	NONE	Issue Dt:		Application #:	11212075	Filing Dt:	08/25/2005
Publication #:	US20070047443	Pub Dt:	03/01/2007
Title:	Channelized flow control

Patent #:	7373486	Issue Dt:	05/13/2008	Application #:	11214193	Filing Dt:	08/29/2005
Publication #:	US20070050602	Pub Dt:	03/01/2007
Title:	PARTIALLY DECODED REGISTER RENAMER

Patent #:	7398361	Issue Dt:	07/08/2008	Application #:	11215604	Filing Dt:	08/30/2005
Publication #:	US20070050564	Pub Dt:	03/01/2007
Title:	COMBINED BUFFER FOR SNOOP, STORE MERGING, LOAD MISS, AND WRITEBACK OPERATIONS

Patent #:	7268633	Issue Dt:	09/11/2007	Application #:	11224256	Filing Dt:	09/12/2005
Publication #:	US20070057735	Pub Dt:	03/15/2007
Title:	VOLTAGE-CONTROLLED OSCILLATOR FOR LOW-VOLTAGE, WIDE FREQUENCY RANGE OPERATION

Patent #:	7707477	Issue Dt:	04/27/2010	Application #:	11238382	Filing Dt:	09/29/2005
Publication #:	US20070074091	Pub Dt:	03/29/2007
Title:	CHECKSUM CALCULATION

Patent #:	7496695	Issue Dt:	02/24/2009	Application #:	11238790	Filing Dt:	09/29/2005
Publication #:	US20070073922	Pub Dt:	03/29/2007
Title:	UNIFIED DMA

Patent #:	7412555	Issue Dt:	08/12/2008	Application #:	11238849	Filing Dt:	09/29/2005
Publication #:	US20070073954	Pub Dt:	03/29/2007
Title:	ORDERING RULE AND FAIRNESS IMPLEMENTATION

Patent #:	7620746	Issue Dt:	11/17/2009	Application #:	11238850	Filing Dt:	09/29/2005
Publication #:	US20070073915	Pub Dt:	03/29/2007
Title:	FUNCTIONAL DMA PERFORMING OPERATION ON DMA DATA AND WRITING RESULT OF OPERATION

Patent #:	7739476	Issue Dt:	06/15/2010	Application #:	11267711	Filing Dt:	11/04/2005
Publication #:	US20070106874	Pub Dt:	05/10/2007
Title:	R AND C BIT UPDATE HANDLING

Patent #:	7411409	Issue Dt:	08/12/2008	Application #:	11281110	Filing Dt:	11/17/2005
Publication #:	US20070109006	Pub Dt:	05/17/2007
Title:	DIGITAL LEAKAGE DETECTOR THAT DETECTS TRANSISTOR LEAKAGE CURRENT IN AN INTEGRATED CIRCUIT

Patent #:	7996662	Issue Dt:	08/09/2011	Application #:	11281832	Filing Dt:	11/17/2005
Publication #:	US20070113060	Pub Dt:	05/17/2007
Title:	FLOATING POINT STATUS/CONTROL REGISTER ENCODINGS FOR SPECULATIVE REGISTER FIELD

Patent #:	7707361	Issue Dt:	04/27/2010	Application #:	11281840	Filing Dt:	11/17/2005
Publication #:	US20070113020	Pub Dt:	05/17/2007
Title:	DATA CACHE BLOCK ZERO IMPLEMENTATION

Patent #:	7529866	Issue Dt:	05/05/2009	Application #:	11282037	Filing Dt:	11/17/2005
Publication #:	US20070130410	Pub Dt:	06/07/2007
Title:	RETRY MECHANISM IN CACHE COHERENT COMMUNICATION AMONG AGENTS

Patent #:	7245150	Issue Dt:	07/17/2007	Application #:	11304165	Filing Dt:	12/15/2005
Publication #:	US20070139075	Pub Dt:	06/21/2007
Title:	COMBINED MULTIPLEXOR/FLOP

Patent #:	7373569	Issue Dt:	05/13/2008	Application #:	11304854	Filing Dt:	12/15/2005
Publication #:	US20070143647	Pub Dt:	06/21/2007
Title:	PULSED FLOP WITH SCAN CIRCUITRY

Patent #:	7319344	Issue Dt:	01/15/2008	Application #:	11304855	Filing Dt:	12/15/2005
Publication #:	US20070139073	Pub Dt:	06/21/2007
Title:	PULSED FLOP WITH EMBEDDED LOGIC

Patent #:	7454674	Issue Dt:	11/18/2008	Application #:	11325123	Filing Dt:	01/04/2006
Publication #:	US20070157057	Pub Dt:	07/05/2007
Title:	DIGITAL JITTER DETECTOR

Patent #:	7493451	Issue Dt:	02/17/2009	Application #:	11453708	Filing Dt:	06/15/2006
Publication #:	US20070294482	Pub Dt:	12/20/2007
Title:	PREFETCH UNIT

Patent #:	7372323	Issue Dt:	05/13/2008	Application #:	11493104	Filing Dt:	07/26/2006
Publication #:	US20070257721	Pub Dt:	11/08/2007
Title:	RESONANCE LIMITER CIRCUITS FOR AN INTEGRATED CIRCUIT

Patent #:	7836220	Issue Dt:	11/16/2010	Application #:	11505736	Filing Dt:	08/17/2006
Publication #:	US20080043732	Pub Dt:	02/21/2008
Title:	NETWORK DIRECT MEMORY ACCESS

Patent #:	7698478	Issue Dt:	04/13/2010	Application #:	11523330	Filing Dt:	09/19/2006
Publication #:	US20080126606	Pub Dt:	05/29/2008
Title:	MANAGED CREDIT UPDATE

Patent #:	7752474	Issue Dt:	07/06/2010	Application #:	11525584	Filing Dt:	09/22/2006
Publication #:	US20080077813	Pub Dt:	03/27/2008
Title:	L1 CACHE FLUSH WHEN PROCESSOR IS ENTERING LOW POWER MODE

Patent #:	NONE	Issue Dt:		Application #:	11545825	Filing Dt:	10/10/2006
Publication #:	US20080086594	Pub Dt:	04/10/2008
Title:	Uncacheable load merging

Patent #:	7472260	Issue Dt:	12/30/2008	Application #:	11546074	Filing Dt:	10/10/2006
Publication #:	US20080086623	Pub Dt:	04/10/2008
Title:	EARLY RETIREMENT OF STORE OPERATION PAST EXCEPTION REPORTING PIPELINE STAGE IN STRONGLY ORDERED PROCESSOR WITH LOAD/STORE QUEUE ENTRY RETAINED UNTIL COMPLETION

Patent #:	7647518	Issue Dt:	01/12/2010	Application #:	11546223	Filing Dt:	10/10/2006
Publication #:	US20080086622	Pub Dt:	04/10/2008
Title:	REPLAY REDUCTION FOR POWER SAVING

Patent #:	7624235	Issue Dt:	11/24/2009	Application #:	11565391	Filing Dt:	11/30/2006
Publication #:	US20080133843	Pub Dt:	06/05/2008
Title:	CACHE USED BOTH AS CACHE AND STAGING BUFFER

Patent #:	7652504	Issue Dt:	01/26/2010	Application #:	11610236	Filing Dt:	12/13/2006
Publication #:	US20080143417	Pub Dt:	06/19/2008
Title:	LOW LATENCY, POWER-DOWN SAFE LEVEL SHIFTER

Patent #:	7548997	Issue Dt:	06/16/2009	Application #:	11620875	Filing Dt:	01/08/2007
Publication #:	US20070130384	Pub Dt:	06/07/2007
Title:	FUNCTIONAL DMA PERFORMING OPERATION ON DMA DATA AND WRITING RESULT OF OPERATION

Patent #:	7779372	Issue Dt:	08/17/2010	Application #:	11627646	Filing Dt:	01/26/2007
Publication #:	US20080180159	Pub Dt:	07/31/2008
Title:	CLOCK GATER WITH TEST FEATURES AND LOW SETUP TIME

Patent #:	7570534	Issue Dt:	08/04/2009	Application #:	11675341	Filing Dt:	02/15/2007
Publication #:	US20080198671	Pub Dt:	08/21/2008
Title:	ENQUEUE EVENT FIRST-IN, FIRST-OUT BUFFER (FIFO)

Patent #:	8069279	Issue Dt:	11/29/2011	Application #:	11682051	Filing Dt:	03/05/2007
Publication #:	US20080222317	Pub Dt:	09/11/2008
Title:	DATA FLOW CONTROL WITHIN AND BETWEEN DMA CHANNELS

Patent #:	7680963	Issue Dt:	03/16/2010	Application #:	11682065	Filing Dt:	03/05/2007
Publication #:	US20070162652	Pub Dt:	07/12/2007
Title:	DMA CONTROLLER CONFIGURED TO PROCESS CONTROL DESCRIPTORS AND TRANSFER DESCRIPTORS

Patent #:	7743279	Issue Dt:	06/22/2010	Application #:	11697428	Filing Dt:	04/06/2007
Publication #:	US20080250275	Pub Dt:	10/09/2008
Title:	PROGRAM COUNTER (PC) TRACE

Patent #:	7836324	Issue Dt:	11/16/2010	Application #:	11740452	Filing Dt:	04/26/2007
Publication #:	US20080195884	Pub Dt:	08/14/2008
Title:	OVERSAMPLING-BASED SCHEME FOR SYNCHRONOUS INTERFACE COMMUNICATION

Patent #:	7652494	Issue Dt:	01/26/2010	Application #:	11753853	Filing Dt:	05/25/2007
Publication #:	US20070229054	Pub Dt:	10/04/2007
Title:	OPERATING AN INTEGRATED CIRCUIT AT A MINIMUM SUPPLY VOLTAGE

Patent #:	7930462	Issue Dt:	04/19/2011	Application #:	11756931	Filing Dt:	06/01/2007
Publication #:	US20080300992	Pub Dt:	12/04/2008
Title:	INTERFACE CONTROLLER THAT HAS FLEXIBLE CONFIGURABILITY AND LOW COST

Patent #:	8284792	Issue Dt:	10/09/2012	Application #:	11756940	Filing Dt:	06/01/2007
Publication #:	US20080298383	Pub Dt:	12/04/2008
Title:	BUFFER MINIMIZATION IN INTERFACE CONTROLLER

Patent #:	7721066	Issue Dt:	05/18/2010	Application #:	11758193	Filing Dt:	06/05/2007
Publication #:	US20080307173	Pub Dt:	12/11/2008
Title:	EFFICIENT ENCODING FOR DETECTING LOAD DEPENDENCY ON STORE WITH MISALIGNMENT

Patent #:	7702858	Issue Dt:	04/20/2010	Application #:	11758219	Filing Dt:	06/05/2007
Publication #:	US20080307168	Pub Dt:	12/11/2008
Title:	LATENCY REDUCTION FOR CACHE COHERENT BUS-BASED CACHE

Patent #:	7836262	Issue Dt:	11/16/2010	Application #:	11758275	Filing Dt:	06/05/2007
Publication #:	US20080307167	Pub Dt:	12/11/2008
Title:	CONVERTING VICTIM WRITEBACK TO A FILL

Patent #:	8239638	Issue Dt:	08/07/2012	Application #:	11758303	Filing Dt:	06/05/2007
Publication #:	US20080307166	Pub Dt:	12/11/2008
Title:	STORE HANDLING IN A PROCESSOR

Patent #:	8055975	Issue Dt:	11/08/2011	Application #:	11758322	Filing Dt:	06/05/2007
Publication #:	US20080307286	Pub Dt:	12/11/2008
Title:	COMBINED SINGLE ERROR CORRECTION/DEVICE KILL DETECTION CODE

Patent #:	8041755	Issue Dt:	10/18/2011	Application #:	11760539	Filing Dt:	06/08/2007
Publication #:	US20080307204	Pub Dt:	12/11/2008
Title:	FAST STATIC ROTATOR/SHIFTER WITH NON TWO'S COMPLEMENTED DECODE AND FAST MASK GENERATION

Patent #:	NONE	Issue Dt:		Application #:	11760547	Filing Dt:	06/08/2007
Publication #:	US20090063609	Pub Dt:	03/05/2009
Title:	Static 4:2 Compressor with Fast Sum and Carryout

Patent #:	8015230	Issue Dt:	09/06/2011	Application #:	11760553	Filing Dt:	06/08/2007
Publication #:	US20080307031	Pub Dt:	12/11/2008
Title:	FAST MODULAR ZERO SUM AND ONES SUM DETERMINATION

Patent #:	7836372	Issue Dt:	11/16/2010	Application #:	11760566	Filing Dt:	06/08/2007
Publication #:	US20080307276	Pub Dt:	12/11/2008
Title:	MEMORY CONTROLLER WITH LOOPBACK TEST INTERFACE

Patent #:	7426601	Issue Dt:	09/16/2008	Application #:	11832841	Filing Dt:	08/02/2007
Publication #:	US20070271402	Pub Dt:	11/22/2007
Title:	SEGMENTED INTERCONNECT FOR CONNECTING MULTIPLE AGENTS IN A SYSTEM

Patent #:	7474571	Issue Dt:	01/06/2009	Application #:	12034071	Filing Dt:	02/20/2008
Publication #:	US20080137448	Pub Dt:	06/12/2008
Title:	INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE

Patent #:	7568087	Issue Dt:	07/28/2009	Application #:	12055016	Filing Dt:	03/25/2008
Publication #:	US20080177988	Pub Dt:	07/24/2008
Title:	PARTIAL LOAD/STORE FORWARD PREDICTION

Patent #:	7752366	Issue Dt:	07/06/2010	Application #:	12263255	Filing Dt:	10/31/2008
Publication #:	US20090055568	Pub Dt:	02/26/2009
Title:	NON-BLOCKING ADDRESS SWITCH WITH SHALLOW PER AGENT QUEUES

Patent #:	7962730	Issue Dt:	06/14/2011	Application #:	12323266	Filing Dt:	11/25/2008
Publication #:	US20090077560	Pub Dt:	03/19/2009
Title:	REPLAYING MEMORY OPERATION ASSIGNED A LOAD/STORE BUFFER ENTRY OCCUPIED BY STORE OPERATION PROCESSED BEYOND EXCEPTION REPORTING STAGE AND RETIRED FROM SCHEDULER

Patent #:	7760559	Issue Dt:	07/20/2010	Application #:	12325476	Filing Dt:	12/01/2008
Publication #:	US20090080268	Pub Dt:	03/26/2009
Title:	INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE

Patent #:	7873762	Issue Dt:	01/18/2011	Application #:	12350008	Filing Dt:	01/07/2009
Publication #:	US20090119531	Pub Dt:	05/07/2009
Title:	DIGITAL PHASE RELATIONSHIP LOCK LOOP

Patent #:	7779208	Issue Dt:	08/17/2010	Application #:	12350020	Filing Dt:	01/07/2009
Publication #:	US20090119488	Pub Dt:	05/07/2009
Title:	PREFETCH UNIT

Patent #:	7991928	Issue Dt:	08/02/2011	Application #:	12408410	Filing Dt:	03/20/2009
Publication #:	US20090177846	Pub Dt:	07/09/2009
Title:	RETRY MECHANISM

Assignor

PA SEMI, INC.

Exec Dt:

05/08/2009

Assignee

APPLE INC.

1 INFINITE LOOP

CUPERTINO, CALIFORNIA 95014

Correspondence name and address
	LAWRENCE J. MERKEL
	P.O. BOX 398
	AUSTIN, TX 78767-0398

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