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Reel/Frame:023525/0835   Pages: 10
Recorded: 11/18/2009
Attorney Dkt #:16113-0001X11
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 58
1
Patent #:
8359187
Issue Dt:
01/22/2013
Application #:
11461420
Filing Dt:
07/31/2006
Publication #:
US20080027702
Pub Dt:
01/31/2008
Title:
SIMULATING A DIFFERENT NUMBER OF MEMORY CIRCUIT DEVICES
2
Patent #:
7609567
Issue Dt:
10/27/2009
Application #:
11461427
Filing Dt:
07/31/2006
Publication #:
US20080025137
Pub Dt:
01/31/2008
Title:
SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
3
Patent #:
7724589
Issue Dt:
05/25/2010
Application #:
11461430
Filing Dt:
07/31/2006
Publication #:
US20080025108
Pub Dt:
01/31/2008
Title:
SYSTEM AND METHOD FOR DELAYING A SIGNAL COMMUNICATED FROM A SYSTEM TO AT LEAST ONE OF A PLURALITY OF MEMORY CIRCUITS
4
Patent #:
NONE
Issue Dt:
Application #:
11461435
Filing Dt:
07/31/2006
Publication #:
US20080025136
Pub Dt:
01/31/2008
Title:
SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION
5
Patent #:
8077535
Issue Dt:
12/13/2011
Application #:
11461437
Filing Dt:
07/31/2006
Publication #:
US20080025122
Pub Dt:
01/31/2008
Title:
A MEMORY REFRESH APPARATUS AND METHOD
6
Patent #:
7580312
Issue Dt:
08/25/2009
Application #:
11461439
Filing Dt:
07/31/2006
Publication #:
US20080031072
Pub Dt:
02/07/2008
Title:
POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS
7
Patent #:
NONE
Issue Dt:
Application #:
11461441
Filing Dt:
07/31/2006
Publication #:
US20080028135
Pub Dt:
01/31/2008
Title:
MULTIPLE-COMPONENT MEMORY INTERFACE SYSTEM AND METHOD
8
Patent #:
7515453
Issue Dt:
04/07/2009
Application #:
11474075
Filing Dt:
06/23/2006
Publication #:
US20070050530
Pub Dt:
03/01/2007
Title:
16
9
Patent #:
NONE
Issue Dt:
Application #:
11474076
Filing Dt:
06/23/2006
Publication #:
US20070014168
Pub Dt:
01/18/2007
Title:
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
10
Patent #:
8796830
Issue Dt:
08/05/2014
Application #:
11515167
Filing Dt:
09/01/2006
Title:
STACKABLE LOW-PROFILE LEAD FRAME PACKAGE
11
Patent #:
8619452
Issue Dt:
12/31/2013
Application #:
11515223
Filing Dt:
09/01/2006
Publication #:
US20070058471
Pub Dt:
03/15/2007
Title:
METHODS AND APPARATUS OF STACKING DRAMS
12
Patent #:
7379316
Issue Dt:
05/27/2008
Application #:
11515406
Filing Dt:
09/01/2006
Publication #:
US20070058410
Pub Dt:
03/15/2007
Title:
METHODS AND APPARATUS OF STACKING DRAMS
13
Patent #:
7392338
Issue Dt:
06/24/2008
Application #:
11524716
Filing Dt:
09/20/2006
Publication #:
US20080025123
Pub Dt:
01/31/2008
Title:
INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS
14
Patent #:
7590796
Issue Dt:
09/15/2009
Application #:
11524811
Filing Dt:
09/20/2006
Publication #:
US20080031030
Pub Dt:
02/07/2008
Title:
SYSTEM AND METHOD FOR POWER MANAGEMENT IN MEMORY SYSTEMS
15
Patent #:
7386656
Issue Dt:
06/10/2008
Application #:
11524812
Filing Dt:
09/20/2006
Publication #:
US20080025125
Pub Dt:
01/31/2008
Title:
INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT
16
Patent #:
NONE
Issue Dt:
Application #:
11538041
Filing Dt:
10/02/2006
Publication #:
US20080082763
Pub Dt:
04/03/2008
Title:
APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF
17
Patent #:
8340953
Issue Dt:
12/25/2012
Application #:
11553372
Filing Dt:
10/26/2006
Publication #:
US20080027697
Pub Dt:
01/31/2008
Title:
MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH POWER SAVING CAPABILITIES
18
Patent #:
9047976
Issue Dt:
06/02/2015
Application #:
11553390
Filing Dt:
10/26/2006
Publication #:
US20080123459
Pub Dt:
05/29/2008
Title:
COMBINED SIGNAL DELAY AND POWER SAVING FOR USE WITH A PLURALITY OF MEMORY CIRCUITS
19
Patent #:
8280714
Issue Dt:
10/02/2012
Application #:
11553399
Filing Dt:
10/26/2006
Publication #:
US20080027703
Pub Dt:
01/31/2008
Title:
MEMORY CIRCUIT SIMULATION SYSTEM AND METHOD WITH REFRESH CAPABILITIES
20
Patent #:
7581127
Issue Dt:
08/25/2009
Application #:
11584179
Filing Dt:
10/20/2006
Publication #:
US20080037353
Pub Dt:
02/14/2008
Title:
INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER SAVING OPERATIONS DURING A COMMAND-RELATED LATENCY
21
Patent #:
8055833
Issue Dt:
11/08/2011
Application #:
11611374
Filing Dt:
12/15/2006
Publication #:
US20080086588
Pub Dt:
04/10/2008
Title:
SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE
22
Patent #:
9542352
Issue Dt:
01/10/2017
Application #:
11672921
Filing Dt:
02/08/2007
Publication #:
US20070204075
Pub Dt:
08/30/2007
Title:
SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
23
Patent #:
9632929
Issue Dt:
04/25/2017
Application #:
11672924
Filing Dt:
02/08/2007
Publication #:
US20070192563
Pub Dt:
08/16/2007
Title:
TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS
24
Patent #:
NONE
Issue Dt:
Application #:
11702960
Filing Dt:
02/05/2007
Publication #:
US20080126690
Pub Dt:
05/29/2008
Title:
Memory module with memory stack
25
Patent #:
8089795
Issue Dt:
01/03/2012
Application #:
11702981
Filing Dt:
02/05/2007
Publication #:
US20070195613
Pub Dt:
08/23/2007
Title:
MEMORY MODULE WITH MEMORY STACK AND INTERFACE WITH ENHANCED CAPABILITIES
26
Patent #:
8041881
Issue Dt:
10/18/2011
Application #:
11762010
Filing Dt:
06/12/2007
Publication #:
US20080056014
Pub Dt:
03/06/2008
Title:
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
27
Patent #:
8090897
Issue Dt:
01/03/2012
Application #:
11762013
Filing Dt:
06/12/2007
Publication #:
US20080062773
Pub Dt:
03/13/2008
Title:
SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
28
Patent #:
8060774
Issue Dt:
11/15/2011
Application #:
11763365
Filing Dt:
06/14/2007
Publication #:
US20080010435
Pub Dt:
01/10/2008
Title:
MEMORY SYSTEMS AND MEMORY MODULES
29
Patent #:
NONE
Issue Dt:
Application #:
11828181
Filing Dt:
07/25/2007
Publication #:
US20080028136
Pub Dt:
01/31/2008
Title:
METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES
30
Patent #:
NONE
Issue Dt:
Application #:
11828182
Filing Dt:
07/25/2007
Publication #:
US20080028137
Pub Dt:
01/31/2008
Title:
Method and Apparatus For Refresh Management of Memory Modules
31
Patent #:
8080874
Issue Dt:
12/20/2011
Application #:
11855826
Filing Dt:
09/14/2007
Title:
PROVIDING ADDITIONAL SPACE BETWEEN AN INTEGRATED CIRCUIT AND A CIRCUIT BOARD FOR POSITIONING A COMPONENT THEREBETWEEN
32
Patent #:
9542353
Issue Dt:
01/10/2017
Application #:
11929225
Filing Dt:
10/30/2007
Publication #:
US20080120443
Pub Dt:
05/22/2008
Title:
SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
33
Patent #:
NONE
Issue Dt:
Application #:
11929261
Filing Dt:
10/30/2007
Publication #:
US20080109595
Pub Dt:
05/08/2008
Title:
REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
34
Patent #:
NONE
Issue Dt:
Application #:
11929286
Filing Dt:
10/30/2007
Publication #:
US20080109206
Pub Dt:
05/08/2008
Title:
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
35
Patent #:
8019589
Issue Dt:
09/13/2011
Application #:
11929320
Filing Dt:
10/30/2007
Publication #:
US20080126692
Pub Dt:
05/29/2008
Title:
MEMORY APPARATUS OPERABLE TO PERFORM A POWER-SAVING OPERATION
36
Patent #:
NONE
Issue Dt:
Application #:
11929403
Filing Dt:
10/30/2007
Publication #:
US20080126687
Pub Dt:
05/29/2008
Title:
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
37
Patent #:
NONE
Issue Dt:
Application #:
11929417
Filing Dt:
10/30/2007
Publication #:
US20080126688
Pub Dt:
05/29/2008
Title:
MEMORY APPARATUS OPERABLE TO PERFORM A REFRESH OPERATION
38
Patent #:
NONE
Issue Dt:
Application #:
11929432
Filing Dt:
10/30/2007
Publication #:
US20080126689
Pub Dt:
05/29/2008
Title:
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
39
Patent #:
NONE
Issue Dt:
Application #:
11929450
Filing Dt:
10/30/2007
Publication #:
US20080103753
Pub Dt:
05/01/2008
Title:
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
40
Patent #:
NONE
Issue Dt:
Application #:
11929483
Filing Dt:
10/30/2007
Publication #:
US20080104314
Pub Dt:
05/01/2008
Title:
A METHOD OF PRESENTING A MEMORY DEVICE HAVING AN EMULATED MEMORY STANDARD
41
Patent #:
8112266
Issue Dt:
02/07/2012
Application #:
11929500
Filing Dt:
10/30/2007
Publication #:
US20080133825
Pub Dt:
06/05/2008
Title:
APPARATUS FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
42
Patent #:
8209479
Issue Dt:
06/26/2012
Application #:
11929571
Filing Dt:
10/30/2007
Publication #:
US20090024789
Pub Dt:
01/22/2009
Title:
MEMORY CIRCUIT SYSTEM AND METHOD
43
Patent #:
8566516
Issue Dt:
10/22/2013
Application #:
11929631
Filing Dt:
10/30/2007
Publication #:
US20080109597
Pub Dt:
05/08/2008
Title:
REFRESH MANAGEMENT OF MEMORY MODULES
44
Patent #:
8244971
Issue Dt:
08/14/2012
Application #:
11929636
Filing Dt:
10/30/2007
Publication #:
US20090024790
Pub Dt:
01/22/2009
Title:
MEMORY CIRCUIT SYSTEM AND METHOD
45
Patent #:
NONE
Issue Dt:
Application #:
11929655
Filing Dt:
10/30/2007
Publication #:
US20080109598
Pub Dt:
05/08/2008
Title:
Method and apparatus for refresh management of memory modules
46
Patent #:
8130560
Issue Dt:
03/06/2012
Application #:
11939432
Filing Dt:
11/13/2007
Title:
MULTI-RANK PARTIAL WIDTH MEMORY MODULES
47
Patent #:
8327104
Issue Dt:
12/04/2012
Application #:
11939440
Filing Dt:
11/13/2007
Publication #:
US20080115006
Pub Dt:
05/15/2008
Title:
ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM
48
Patent #:
8111566
Issue Dt:
02/07/2012
Application #:
11941589
Filing Dt:
11/16/2007
Title:
OPTIMAL CHANNEL DESIGN FOR MEMORY DEVICES FOR PROVIDING A HIGH-SPEED MEMORY INTERFACE
49
Patent #:
7599205
Issue Dt:
10/06/2009
Application #:
12055107
Filing Dt:
03/25/2008
Publication #:
US20080170425
Pub Dt:
07/17/2008
Title:
METHODS AND APPARATUS OF STACKING DRAMS
50
Patent #:
8397013
Issue Dt:
03/12/2013
Application #:
12057306
Filing Dt:
03/27/2008
Title:
HYBRID MEMORY MODULE
51
Patent #:
7761724
Issue Dt:
07/20/2010
Application #:
12111819
Filing Dt:
04/29/2008
Publication #:
US20080239857
Pub Dt:
10/02/2008
Title:
INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT
52
Patent #:
7730338
Issue Dt:
06/01/2010
Application #:
12111828
Filing Dt:
04/29/2008
Publication #:
US20080239858
Pub Dt:
10/02/2008
Title:
INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS
53
Patent #:
8386722
Issue Dt:
02/26/2013
Application #:
12144396
Filing Dt:
06/23/2008
Title:
STACKED DIMM MEMORY INTERFACE
54
Patent #:
8081474
Issue Dt:
12/20/2011
Application #:
12203100
Filing Dt:
09/02/2008
Title:
EMBOSSED HEAT SPREADER
55
Patent #:
8438328
Issue Dt:
05/07/2013
Application #:
12378328
Filing Dt:
02/14/2009
Publication #:
US20090216939
Pub Dt:
08/27/2009
Title:
EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMS
56
Patent #:
8949519
Issue Dt:
02/03/2015
Application #:
12507682
Filing Dt:
07/22/2009
Publication #:
US20090285031
Pub Dt:
11/19/2009
Title:
SIMULATING A MEMORY CIRCUIT
57
Patent #:
8335894
Issue Dt:
12/18/2012
Application #:
12508496
Filing Dt:
07/23/2009
Title:
CONFIGURABLE MEMORY SYSTEM WITH INTERFACE CIRCUIT
58
Patent #:
7990746
Issue Dt:
08/02/2011
Application #:
12510134
Filing Dt:
07/27/2009
Publication #:
US20090290442
Pub Dt:
11/26/2009
Title:
METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES
Assignor
1
METARAM, INC.
Exec Dt:
09/11/2009
Assignee
1
GOOGLE INC.
1600 AMPHITHEATRE PARKWAY
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
HANS TROESCH
FISH & RICHARDSON P.C.
P.O.BOX 1022
MINNEAPOLIS, MN 55440-1022

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