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Patent Assignment Details
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Reel/Frame:023786/0416   Pages: 274
Recorded: 01/04/2010
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3434
Page 20 of 35
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
1
Patent #:
Issue Dt:
11/12/2002
Application #:
09917977
Filing Dt:
07/30/2001
Publication #:
Pub Dt:
11/15/2001
Title:
SYSTEM FOR ISSUING DEVICE REQUESTS BY PROXY
2
Patent #:
Issue Dt:
09/03/2002
Application #:
09918276
Filing Dt:
07/30/2001
Publication #:
Pub Dt:
11/22/2001
Title:
MEMORY DEVICE WITH SYNCHRONIZED OUTPUT PATH
3
Patent #:
Issue Dt:
12/17/2002
Application #:
09919327
Filing Dt:
07/31/2001
Publication #:
Pub Dt:
01/17/2002
Title:
ELIMINATION OF PRECHARGE OPERATION IN SYNCHRONOUS FLASH MEMORY
4
Patent #:
Issue Dt:
07/22/2003
Application #:
09920166
Filing Dt:
08/01/2001
Publication #:
Pub Dt:
01/31/2002
Title:
256 MEG DYNAMIC RANDOM ACCESS MEMORY
5
Patent #:
Issue Dt:
06/29/2004
Application #:
09920780
Filing Dt:
08/01/2001
Publication #:
Pub Dt:
05/02/2002
Title:
MEMORY DEVICE WITH PIPELINED ADDRESS PATH
6
Patent #:
Issue Dt:
02/18/2003
Application #:
09920866
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
02/06/2003
Title:
PROGRAMMING METHODS FOR MULTI-LEVEL FLASH EEPROMS
7
Patent #:
Issue Dt:
03/18/2003
Application #:
09920970
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
01/03/2002
Title:
METHODS OF WAFER LEVEL FABRICATION AND ASSEMBLY OF CHIP SCALE PACKAGES
8
Patent #:
Issue Dt:
07/30/2002
Application #:
09921205
Filing Dt:
08/02/2001
Publication #:
Pub Dt:
01/03/2002
Title:
MASK REPATTERN PROCESS
9
Patent #:
Issue Dt:
09/28/2004
Application #:
09921614
Filing Dt:
08/03/2001
Publication #:
Pub Dt:
02/20/2003
Title:
A SYSTEM AND METHOD TO IMPROVE THE EFFICIENCY OF SYNCHRONOUS MIRROR DELAYS AND DELAY LOCKED LOOPS
10
Patent #:
Issue Dt:
05/23/2006
Application #:
09923058
Filing Dt:
08/06/2001
Publication #:
Pub Dt:
01/03/2002
Title:
METHOD FOR ENHANCING SILICON DIOXIDE TO SILICON NITRIDE SELECTIVITY
11
Patent #:
Issue Dt:
04/29/2003
Application #:
09923136
Filing Dt:
08/06/2001
Publication #:
Pub Dt:
02/06/2003
Title:
METHOD AND APPARATUS FOR DETERMINING DIGITAL DELAY LINE ENTRY POINT
12
Patent #:
Issue Dt:
07/16/2002
Application #:
09924066
Filing Dt:
08/07/2001
Publication #:
Pub Dt:
12/06/2001
Title:
METHOD AND APPARATUS FOR MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
13
Patent #:
Issue Dt:
11/05/2002
Application #:
09924139
Filing Dt:
08/07/2001
Publication #:
Pub Dt:
01/10/2002
Title:
METHOD AND APPARATUS FOR GENERATING EXPECT DATA FROM A CAPTURED BIT PATTERN, AND MEMORY DEVICE USING SAME
14
Patent #:
Issue Dt:
07/06/2004
Application #:
09924214
Filing Dt:
08/07/2001
Publication #:
Pub Dt:
03/21/2002
Title:
METHOD AND SYSTEM FOR ESTABLISHING A SECURITY PERIMETER IN COMPUTER NETWORKS
15
Patent #:
Issue Dt:
08/20/2002
Application #:
09924363
Filing Dt:
08/07/2001
Publication #:
Pub Dt:
03/07/2002
Title:
ADJUSTABLE OUTPUT DRIVER CIRCUIT
16
Patent #:
Issue Dt:
06/17/2003
Application #:
09924648
Filing Dt:
08/08/2001
Title:
256 MEG DYNAMIC RANDOM ACCESS MEMORY
17
Patent #:
Issue Dt:
11/04/2003
Application #:
09925079
Filing Dt:
08/07/2001
Publication #:
Pub Dt:
03/07/2002
Title:
MIXED ENCLAVE OPERATION IN A COMPUTER NETWORK
18
Patent #:
Issue Dt:
03/04/2003
Application #:
09925237
Filing Dt:
08/08/2001
Publication #:
Pub Dt:
03/07/2002
Title:
METHOD FOR WRITING TO MULTIPLE BANKS OF A MEMORY DEVICE
19
Patent #:
Issue Dt:
09/23/2003
Application #:
09928621
Filing Dt:
08/13/2001
Publication #:
Pub Dt:
02/13/2003
Title:
SYNCHRONOUS FLASH MEMORY WITH VIRTUAL SEGMENT ARCHITECTURE
20
Patent #:
Issue Dt:
01/06/2004
Application #:
09930344
Filing Dt:
08/15/2001
Title:
256 MEG DYNAMIC RANDOM ACCESS MEMORY
21
Patent #:
Issue Dt:
07/23/2002
Application #:
09930761
Filing Dt:
08/14/2001
Title:
METHOD AND APPARATUS FOR MULTIPLE LATENCY SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
22
Patent #:
Issue Dt:
09/17/2002
Application #:
09930762
Filing Dt:
08/15/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD AND APPARATUS FOR MULTIPLE LATENCY SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
23
Patent #:
Issue Dt:
10/21/2003
Application #:
09930961
Filing Dt:
08/17/2001
Publication #:
Pub Dt:
12/20/2001
Title:
DRAM CAPACITOR FORMULATION USING A DOUBLE-SIDED ELECTRODE
24
Patent #:
Issue Dt:
09/16/2003
Application #:
09931728
Filing Dt:
08/16/2001
Publication #:
Pub Dt:
01/31/2002
Title:
SYSTEM AND METHOD OF PROCESSING MEMORY REQUESTS IN A PIPELINED MEMORY CONTROLLER
25
Patent #:
Issue Dt:
08/20/2002
Application #:
09932068
Filing Dt:
08/17/2001
Publication #:
Pub Dt:
12/13/2001
Title:
METHOD AND APPARATUS FOR IMPROVED STORAGE OF COMPUTER SYSTEM CONFIGURATION INFORMATION
26
Patent #:
Issue Dt:
06/17/2003
Application #:
09932080
Filing Dt:
08/17/2001
Publication #:
Pub Dt:
12/20/2001
Title:
METHOD AND APPARATUS FOR COUPLING A SEMICONDUCTOR DIE TO DIE TERMINALS
27
Patent #:
Issue Dt:
05/28/2002
Application #:
09932242
Filing Dt:
08/17/2001
Publication #:
Pub Dt:
03/07/2002
Title:
RECONFIGURABLE MEMORY WITH SELECTABLE ERROR CORRECTION STORAGE
28
Patent #:
Issue Dt:
10/01/2002
Application #:
09933913
Filing Dt:
08/20/2001
Title:
METHODS OF FORMING CAPACITOR ELECTRODES
29
Patent #:
Issue Dt:
03/16/2004
Application #:
09934094
Filing Dt:
08/21/2001
Publication #:
Pub Dt:
11/06/2003
Title:
STACKED LEADS-OVER CHIP MULTI-CHIP MODULE
30
Patent #:
Issue Dt:
08/20/2002
Application #:
09934220
Filing Dt:
08/20/2001
Publication #:
Pub Dt:
02/28/2002
Title:
ACTIVE TERMINATE COMMAND IN SYNCHRONOUS FLASH MEMORY
31
Patent #:
Issue Dt:
07/20/2004
Application #:
09934784
Filing Dt:
08/22/2001
Publication #:
Pub Dt:
12/27/2001
Title:
ON-CHIP SUBSTRATE REGULATOR TEST MODE
32
Patent #:
Issue Dt:
12/21/2004
Application #:
09935086
Filing Dt:
08/22/2001
Publication #:
Pub Dt:
12/20/2001
Title:
ON-CHIP SUBSTRATE REGULATOR TEST MODE
33
Patent #:
Issue Dt:
11/23/2004
Application #:
09935232
Filing Dt:
08/22/2001
Publication #:
Pub Dt:
12/13/2001
Title:
ON-CHIP SUBSTRATE REGULATOR TEST MODE
34
Patent #:
Issue Dt:
07/20/2004
Application #:
09938394
Filing Dt:
08/23/2001
Publication #:
Pub Dt:
02/27/2003
Title:
BOTTOM ANTIREFLECTION COATING COLOR FILTER PROCESS FOR FABRICATING SOLID STATE IMAGE SENSORS
35
Patent #:
Issue Dt:
09/16/2003
Application #:
09938461
Filing Dt:
08/21/2001
Publication #:
Pub Dt:
07/04/2002
Title:
RECOVERY OF USEFUL AREAS OF PARTIALLY DEFECTIVE SYNCHRONOUS MEMORY COMPONENTS
36
Patent #:
Issue Dt:
12/17/2002
Application #:
09938809
Filing Dt:
08/24/2001
Publication #:
Pub Dt:
06/13/2002
Title:
METHODS AND APPARATUS FOR READING MEMORY DEVICE REGISTER DATA
37
Patent #:
Issue Dt:
02/03/2004
Application #:
09939653
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
03/06/2003
Title:
MEMORY DEVICE HAVING SELECTABLE CLOCK INPUT AND METHOD FOR OPERATING SAME
38
Patent #:
Issue Dt:
08/15/2006
Application #:
09939848
Filing Dt:
08/27/2001
Publication #:
Pub Dt:
01/03/2002
Title:
FIELD EMISSION TIPS, ARRAYS, AND DEVICES
39
Patent #:
Issue Dt:
03/11/2003
Application #:
09939849
Filing Dt:
08/27/2001
Publication #:
Pub Dt:
01/24/2002
Title:
VERTICALLY MOUNTABLE SEMICONDUCTOR DEVICE, ASSEMBLY, AND METHODS
40
Patent #:
Issue Dt:
04/15/2003
Application #:
09939919
Filing Dt:
08/27/2001
Publication #:
Pub Dt:
01/10/2002
Title:
ELECTRICAL AND THERMAL CONTACT FOR USE IN SEMICONDUCTOR DEVICES
41
Patent #:
Issue Dt:
09/05/2006
Application #:
09940259
Filing Dt:
08/27/2001
Publication #:
Pub Dt:
06/20/2002
Title:
LOGIC AND MEMORY DEVICE INTEGRATION
42
Patent #:
Issue Dt:
12/30/2003
Application #:
09940824
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
02/21/2002
Title:
METAL OXYNITRIDE CAPACITOR BARRIER LAYER
43
Patent #:
Issue Dt:
09/06/2005
Application #:
09940917
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
02/14/2002
Title:
CHEMICAL VAPOR DEPOSITION OF TITANIUM
44
Patent #:
Issue Dt:
08/27/2002
Application #:
09940979
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
04/18/2002
Title:
FLASH MEMORY WITH OVERERASE PROTECTION
45
Patent #:
Issue Dt:
12/14/2004
Application #:
09940980
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
01/17/2002
Title:
CHEMICAL VAPOR DEPOSITION OF TITANIUM
46
Patent #:
Issue Dt:
06/07/2005
Application #:
09941123
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
01/03/2002
Title:
CHEMICAL VAPOR DEPOSITION OF TITANIUM
47
Patent #:
Issue Dt:
12/14/2004
Application #:
09941125
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
01/03/2002
Title:
CHEMICAL VAPOR DEPOSITION OF TITANIUM
48
Patent #:
Issue Dt:
10/26/2004
Application #:
09941647
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF TRANSFERRING DATA INTERNALLY WITHOUT USING AN EXTERNAL BUS
49
Patent #:
Issue Dt:
03/25/2003
Application #:
09941649
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
DRAM ACTIVE TERMINATION CONTROL
50
Patent #:
Issue Dt:
04/19/2005
Application #:
09942183
Filing Dt:
08/29/2001
Publication #:
Pub Dt:
03/06/2003
Title:
ROUTING ELEMENT FOR USE IN MULTI-CHIP MODULES, MULTI-CHIP MODULES INCLUDING THE ROUTING ELEMENT, AND METHODS
51
Patent #:
Issue Dt:
06/21/2005
Application #:
09942898
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/13/2003
Title:
ZERO POWER CHIP STANDBY MODE
52
Patent #:
Issue Dt:
06/06/2006
Application #:
09943320
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
MEMORY CONTROLLERS HAVING PINS WITH SELECTABLE FUNCTIONALITY
53
Patent #:
Issue Dt:
05/27/2003
Application #:
09943330
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
FLASH MEMORY WITH DDRAM INTERFACE
54
Patent #:
Issue Dt:
04/25/2006
Application #:
09943475
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
FLASH MEMORY WITH DATA DECOMPRESSION
55
Patent #:
Issue Dt:
04/25/2006
Application #:
09943476
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
PROCESSING SYSTEM WITH DIRECT MEMORY TRANSFER
56
Patent #:
Issue Dt:
02/01/2005
Application #:
09943779
Filing Dt:
08/29/2001
Publication #:
Pub Dt:
03/06/2003
Title:
VARIABLE DELAY CIRCUIT AND METHOD, AND DELAY LOCKED LOOP, MEMORY DEVICE AND COMPUTER SYSTEM USING SAME
57
Patent #:
Issue Dt:
08/31/2004
Application #:
09943880
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METHOD OF FABRICATION OF STACKED SEMICONDUCTOR DEVICES
58
Patent #:
Issue Dt:
01/20/2004
Application #:
09943999
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/14/2002
Title:
LASER MARKING TECHNIQUES FOR BARE SEMICONDUCTOR DIE
59
Patent #:
Issue Dt:
12/03/2002
Application #:
09944132
Filing Dt:
09/04/2001
Publication #:
Pub Dt:
04/18/2002
Title:
SEMICONDUCTOR DEVICES HAVING MIRRORED TERMINAL ARRANGEMENTS, DEVICES INCLUDING SAME, AND METHODS OF TESTING SUCH SEMICONDUCTOR DEVICES
60
Patent #:
Issue Dt:
05/18/2004
Application #:
09944237
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/20/2003
Title:
METHOD AND APPARATUS FOR PROVIDING CLOCK SIGNALS AT DIFFERENT LOCATIONS WITH MINIMAL CLOCK SKEW
61
Patent #:
Issue Dt:
05/21/2002
Application #:
09944257
Filing Dt:
08/29/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METHOD AND APPARATUS FOR MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
62
Patent #:
Issue Dt:
04/15/2003
Application #:
09944512
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
05/02/2002
Title:
STACKABLE BALL GRID ARRAY PACKAGE
63
Patent #:
Issue Dt:
11/16/2004
Application #:
09944798
Filing Dt:
08/29/2001
Publication #:
Pub Dt:
04/18/2002
Title:
METHOD AND APPARATUS FOR PLANARIZING AND CLEANING MICROELECTRONIC SUBSTRATES
64
Patent #:
Issue Dt:
08/26/2003
Application #:
09944894
Filing Dt:
08/31/2001
Publication #:
Pub Dt:
04/25/2002
Title:
METHOD OF FORMING A LOCAL INTERCONNECT
65
Patent #:
Issue Dt:
07/20/2004
Application #:
09944937
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
GRAPHICS RESAMPLING SYSTEM AND METHOD FOR USE THEREOF
66
Patent #:
Issue Dt:
12/05/2006
Application #:
09945367
Filing Dt:
08/31/2001
Publication #:
Pub Dt:
03/06/2003
Title:
SYSTEM AND METHOD FOR MULTI-SAMPLING PRIMITIVES TO REDUCE ALIASING
67
Patent #:
Issue Dt:
09/20/2005
Application #:
09945397
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/14/2002
Title:
CONDUCTIVE CONTAINER STRUCTURES HAVING A DIELECTRIC CAP
68
Patent #:
Issue Dt:
12/21/2004
Application #:
09945497
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/14/2002
Title:
CONDUCTIVE CONTAINER STRUCTURES HAVING A DIELECTRIC CAP
69
Patent #:
Issue Dt:
10/03/2006
Application #:
09945515
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
APPARATUS, METHOD, AND PRODUCT FOR DOWNSCALING AN IMAGE
70
Patent #:
Issue Dt:
05/03/2005
Application #:
09945555
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
CAPACITOR FOR USE IN AN INTEGRATED CIRCUIT
71
Patent #:
Issue Dt:
09/07/2004
Application #:
09952897
Filing Dt:
09/11/2001
Publication #:
Pub Dt:
04/25/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITY
72
Patent #:
Issue Dt:
01/07/2003
Application #:
09954675
Filing Dt:
09/17/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METHOD FOR ADJUSTING AN OUTPUT SLEW RATE OF A BUFFER
73
Patent #:
Issue Dt:
11/30/2004
Application #:
09955632
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
08/15/2002
Title:
METHODS OF FORMING CAPACITORS
74
Patent #:
Issue Dt:
08/06/2002
Application #:
09957112
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
02/07/2002
Title:
WEB-FORMAT PLANARIZING MACHINES AND METHODS FOR PLANARIZING MICROELECTRONIC SUBSTRATE ASSEMBLIES
75
Patent #:
Issue Dt:
06/24/2003
Application #:
09957733
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
04/18/2002
Title:
READ COMPRESSION IN A MEMORY
76
Patent #:
Issue Dt:
09/24/2002
Application #:
09957777
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
03/21/2002
Title:
SYNCHRONOUS MEMORY STATUS REGISTER
77
Patent #:
Issue Dt:
10/01/2002
Application #:
09957833
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
03/28/2002
Title:
METHOD AND CIRCUITRY FOR BANK TRACKING IN WRITE COMMAND SEQUENCE
78
Patent #:
Issue Dt:
01/21/2003
Application #:
09961204
Filing Dt:
09/21/2001
Title:
RADIO FREQUENCY DATA COMMUNICATIONS DEVICE WITH ADJUSTABLE RECEIVER SENSITIVITY AND METHOD
79
Patent #:
Issue Dt:
11/30/2004
Application #:
09963842
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
01/24/2002
Title:
METHOD FOR FABRICATING A MEMORY CHIP
80
Patent #:
Issue Dt:
07/23/2002
Application #:
09964145
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
02/07/2002
Title:
CONTROLLABLE OVONIC PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE AND METHODS OF FABRICATING THE SAME
81
Patent #:
Issue Dt:
07/16/2002
Application #:
09965298
Filing Dt:
09/26/2001
Publication #:
Pub Dt:
01/24/2002
Title:
WEB-FORMAT PLANARIZING MACHINES AND METHODS FOR PLANARIZING MICROELECTRONIC SUBSTRATE ASSEMBLIES
82
Patent #:
Issue Dt:
05/04/2004
Application #:
09968564
Filing Dt:
10/01/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD OF FORMING A NON-CONTINUOUS CONDUCTIVE LAYER FOR LAMINATED SUBSTRATES
83
Patent #:
Issue Dt:
10/15/2002
Application #:
09971723
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
02/07/2002
Title:
SYSTEM FOR REAL-TIME CONTROL OF SEMICONDUCTOR WAFER POLISHING
84
Patent #:
Issue Dt:
10/08/2002
Application #:
09971819
Filing Dt:
10/03/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHODS OF FORMING A CIRCUIT AND METHODS OF PREPARING AN INTEGRATED CIRCUIT
85
Patent #:
Issue Dt:
01/31/2006
Application #:
09972489
Filing Dt:
10/05/2001
Title:
METHOD AND APPARATUS FOR ELECTRONIC IMAGE PROCESSING
86
Patent #:
Issue Dt:
11/11/2003
Application #:
09973998
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
04/10/2003
Title:
METHOD AND CIRCUIT FOR ADJUSTING A SELF-REFRESH RATE TO MAINTAIN DYNAMIC DATA AT LOW SUPPLY VOLTAGES
87
Patent #:
Issue Dt:
12/24/2002
Application #:
09974001
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
03/07/2002
Title:
CIRCUIT, METHOD OF ADHERING AN INTEGRATED CIRCUIT DEVICE TO A SUBSTRATE, AND METHOD OF FORMING A CIRCUIT
88
Patent #:
Issue Dt:
08/12/2003
Application #:
09974322
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
04/10/2003
Title:
METHOD AND CIRCUIT FOR ADJUSTING THE TIMING OF OUPUT DATA BASED ON AN OPERATIONAL MODE OF OUTPUT DRIVERS
89
Patent #:
Issue Dt:
05/27/2003
Application #:
09974343
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
03/07/2002
Title:
METHOD AND APPARATUS FOR CLEANING A SURFACE OF A MICROELECTRONIC SUBSTRATE
90
Patent #:
Issue Dt:
12/09/2003
Application #:
09977398
Filing Dt:
10/16/2001
Publication #:
Pub Dt:
03/28/2002
Title:
SYNCHRONOUS DRAM MODULES WITH MULTIPLE CLOCK OUT SIGNALS
91
Patent #:
Issue Dt:
05/27/2003
Application #:
09977456
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
04/17/2003
Title:
ASSEMBLIES INCLUDING STACKED SEMICONDUCTOR DEVICES SEPARATED A DISTANCE DEFINED BY ADHESIVE MATERIAL INTERPOSED THEREBETWEEN, PACKAGES INCLUDING THE ASSEMBLIES, AND METHODS
92
Patent #:
Issue Dt:
04/06/2004
Application #:
09981549
Filing Dt:
10/17/2001
Publication #:
Pub Dt:
02/28/2002
Title:
SHALLOW DOPED JUNCTIONS WITH A VARIABLE PROFILE GRADATION OF DOPANTS
93
Patent #:
Issue Dt:
11/12/2002
Application #:
09983905
Filing Dt:
10/26/2001
Publication #:
Pub Dt:
04/25/2002
Title:
METHOD AND APPARATUS FOR INDEPENDENT OUTPUT DRIVER CALIBRATION
94
Patent #:
Issue Dt:
09/12/2006
Application #:
09988485
Filing Dt:
11/20/2001
Publication #:
Pub Dt:
06/20/2002
Title:
COMMUNICATION DEVICES, REMOTE INTELLIGENT COMMUNICATION DEVICES, ELECTRONIC COMMUNICATION DEVICES, METHODS OF FORMING REMOTE INTELLIGENT COMMUNICATION DEVICES AND METHODS OF FORMING A RADIO FREQUENCY IDENTIFICATION DEVICE
95
Patent #:
Issue Dt:
11/18/2003
Application #:
09988988
Filing Dt:
11/19/2001
Publication #:
Pub Dt:
05/22/2003
Title:
PARTIAL ARRAY SELF-REFRESH
96
Patent #:
Issue Dt:
12/08/2009
Application #:
09989372
Filing Dt:
11/21/2001
Publication #:
Pub Dt:
04/25/2002
Title:
ELECTROPOLISHED PATTERNED METAL LAYER FOR SEMICONDUCTOR DEVICES
97
Patent #:
Issue Dt:
04/26/2005
Application #:
09989960
Filing Dt:
11/21/2001
Publication #:
Pub Dt:
03/28/2002
Title:
A BATTERY POWERABLE APPARATUS, RADIO FREQUENCY COMMUNICATION DEVICE, AND ELECTRIC CIRCUIT
98
Patent #:
Issue Dt:
10/04/2005
Application #:
09991198
Filing Dt:
11/20/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METHOD AND APPARATUS FOR GENERATING A PHASE DEPENDENT CONTROL SIGNAL
99
Patent #:
Issue Dt:
12/03/2002
Application #:
09993010
Filing Dt:
11/14/2001
Publication #:
Pub Dt:
03/21/2002
Title:
SYSTEM FOR REAL-TIME CONTROL OF SEMICONDUCTOR WAFER POLISHING
100
Patent #:
Issue Dt:
02/10/2004
Application #:
09993109
Filing Dt:
11/13/2001
Publication #:
Pub Dt:
06/20/2002
Title:
SEMICONDUCTOR ASSEMBLIES, METHODS OF FORMIGN STRUCTURES OVER SEMICONDUCTOR SUBSTRATES, AND METHODS OF FORMING TRANSISTORS ASSOCIATED WITH SEMICONDUCTOR SUBSTRATES
Assignor
1
Exec Dt:
12/23/2009
Assignee
1
26 DEER CREEK LANE
MT. KISCO, NEW YORK 10549
Correspondence name and address
CHRISTOPHER C. HENRY
ROPES & GRAY LLP
1211 AVENUE OF THE AMERICAS
NEW YORK, NEW YORK 10036

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